System having configurable interfaces for flexible system configurations

Abstract

An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.

1 . An apparatus comprising:
 a plurality of systems, in which each of the plurality of systems includes at least one processor, a cache, a data interface circuit to receive and send data, and a memory controller, wherein each memory controller is to operate with a respective memory, and in which each of the plurality of systems is coupled to at least one other one of the plurality of systems for bi-directional data transfer, wherein each of the plurality of systems further includes a coherent agent to enforce coherency across the plurality of systems for at least some accesses, the plurality of systems including at least one system to bi-directionally receive and transmit packets to and from a network; and   a switch interface circuit coupled to operate as a switch interface between one or more systems and a switch fabric, wherein the switch interface circuit bi-directionally receives and transmits packets between the one or more systems coupled to the switch interface circuit and the switch fabric.   
   
   
       2 . The apparatus of  claim 1  further comprising a port aggregator circuit to couple one or more systems to the network in order to receive and transmit packets through a plurality of network ports. 
   
   
       3 . The apparatus of  claim 2  wherein the port aggregator circuit is to aggregate packets transferred through the network ports. 
   
   
       4 . The apparatus of  claim 1  further comprising a coprocessor coupled to one of the plurality of systems. 
   
   
       5 . The apparatus of  claim 4  wherein the coprocessor is to assist in processing packets. 
   
   
       6 . The apparatus of  claim 4  wherein the coprocessor is to perform a lookup function. 
   
   
       7 . The apparatus of  claim 4  wherein the coprocessor is to perform security processing on a packet. 
   
   
       8 . The apparatus of  claim 1  wherein each of the plurality of systems is integrated onto a separate integrated circuit chip. 
   
   
       9 . The apparatus of  claim 1  wherein at least one system is coupled to an input/output (I/O) interface. 
   
   
       10 . The apparatus of  claim 9  wherein the at least one system that is coupled to the I/O interface is to receive and transmit packets with the I/O interface through a bridge. 
   
   
       11 . The apparatus of  claim 9  wherein the at least one system that is coupled to the I/O interface is to receive and transmit packets with the I/O interface through the data interface circuit. 
   
   
       12 . The apparatus of  claim 1  wherein the at least one system to receive and transmit packets to and from the network is disposed on a first circuit card, and wherein at least one other one of the plurality of systems is disposed on a second circuit card. 
   
   
       13 . A method comprising:
 receiving packet data from a first network coupled to a first line card having a plurality of systems, in which each of the plurality of systems includes at least one processor, a cache, a data interface circuit to receive and send data, and a memory controller, wherein each memory controller is to operate with a respective memory, and in which each of the plurality of systems is coupled to at least one other one of the plurality of systems for bi-directional data transfer, wherein each of the plurality of systems further includes a coherent agent to enforce coherency across the plurality of systems for at least some accesses, the plurality of systems including at least one system to bi-directionally receive and transmit packets to and from the first network;   transferring the packet data to a switch interface circuit coupled to operate as a switch interface between one or more systems of the first line card and a switch fabric, wherein the switch interface circuit bi-directionally receives and transmits packets between the one or more systems coupled to the switch interface circuit and the switch fabric;   transferring the packet data to the switch fabric; and   transferring the packet data from the switch fabric to a second line card coupled to the switch fabric to transmit the packet data on a second network coupled to the second line card.   
   
   
       14 . The method of  claim 13  further comprising using a port aggregator circuit on the first line card to couple one or more systems of the first line card to the first network in order to receive and transmit packets through a plurality of network ports. 
   
   
       15 . The method of  claim 14  wherein using the port aggregator circuit includes aggregating packets transferred through the network ports. 
   
   
       16 . The method of  claim 13  further comprising using a coprocessor coupled to one of the plurality of systems to coprocess the packet data. 
   
   
       17 . The method of  claim 16  wherein using the coprocessor includes performing a lookup function. 
   
   
       18 . The method of  claim 16  wherein using the coprocessor includes performing a security processing on a packet.