Semiconductor testing instrument to determine safe operating area

Abstract

An instrument for determination of the dc safe area of operation of a semiconductor device-under-test comprises a means to apply an adjustable bias at the input of a device-under-test, wherein the means comprises a dc biaser to apply a dc bias at a bias point within the safe operating limit, and a variable biaser subsequently to apply a variable bias comprising fast, superimposed rectangular bipolar pulses, and wherein the instrument further comprises means to measure the current response thereto so as to permit extrapolation of a detailed I-V response in the vicinity of the safe operating limit. A method of determination of the dc safe area of operation of a semiconductor device-under-test is also described.

1 . An instrument for determination of the dc safe area of operation of a semiconductor device-under-test comprises a first dc biaser to apply an adjustable dc bias at a first channel of a device-under-test, and a means to apply a bias signal at a second channel of a device-under-test which means comprises a second dc biaser to apply a dc bias at a bias point within the safe operating limit, and a variable biaser subsequently to apply a variable stimulus comprising fast, superimposed rectangular bipolar pulses, and wherein the instrument further comprises means to measure the current response thereto so as to permit extrapolation of a detailed I-V response in the vicinity of the safe operating limit. 
   
   
       2 . An instrument in accordance with  claim 1  wherein the variable biaser generates pulses with progressively increasing amplitude. 
   
   
       3 . An instrument in accordance with  claim 1  wherein the variable biaser generates a pulsed wave form that is essentially critically damped so as to achieve a minimum rise time up to the point where the pulses become substantially flat. 
   
   
       4 . An instrument in accordance with  claim 1  wherein the variable biaser generates a pulsed wave form with a pulse length below about one μs. 
   
   
       5 . An instrument in accordance with  claim 4  wherein the variable biaser generates a pulsed wave form with a pulse length below about 100 ns. 
   
   
       6 . An instrument in accordance with  claim 1  wherein the means to apply the adjustable bias at the input comprises a high stability voltage source serially connected to the input via a resistor. 
   
   
       7 . A measuring instrument in accordance with  claim 6  wherein the high stability voltage source is further serially connected through a low pass filter. 
   
   
       8 . A measuring instrument in accordance with  claim 7  wherein the resistance is followed by a combination of series inductors and shunt capacitors to form the low pass filter. 
   
   
       9 . A measuring instrument in accordance with  claim 1 , further comprising a remote head including at least the response measuring means, into which the device-under-test may be directly connected. 
   
   
       10 . A measuring instrument in accordance with  claim 1 , further comprising a remote head including at least means to generate the superimposed fast, generally rectangular, synchronous bipolar pulses, into which the device-under-test may be directly connected. 
   
   
       11 . A method for determination of the dc safe area of operation of a semiconductor device-under-test comprising the steps of:
 applying a dc bias at a first channel such as the input of the device-under-test;   applying a dc bias at a second channel such as the output of the device-under-test at a bias point base level within the safe operating limit of the device-under-test;   applying a variable stimulus at the second channel comprising superimposed fast rectangular bipolar pulses;   rapidly measuring the current response thereto at both the channels;   extrapolating from the responses a detailed I-V response for the device in the vicinity of the safe operating limit.   
   
   
       12 . A method in accordance with  claim 11  wherein the variable bias is applied in the form of pulses with progressively increasing amplitude. 
   
   
       13 . A method for determination of the dc safe area of operation of a semiconductor device-under-test comprising the repeated performance of the steps in accordance with  claim 11  as an iterative succession. 
   
   
       14 . A method in accordance with  claim 13  comprising the steps of:
 applying an initial dc bias at a point known to be well within the safe operating area of the device-under-test;   superimposing a pulsed bias and in particular a pulsed bias of progressively increased amplitude;   detecting incipient breakdown and removing the pulsed bias;   determining a second dc biasing point nearer to but safely below the breakdown point as identified hereinbefore;   repeating the process steps above until a sufficiently accurate characterisation of the breakdown point is obtained.