Method of manufacturing non-volatile memory

Abstract

A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

1 . A method of fabricating a non-volatile memory, comprising:
 providing a substrate;   forming a plurality of stacked gate structures on the substrate, wherein the stacked gate structures are separated from each other by a gap and each stacked gate structure comprises a gate dielectric layer, a first conductive layer, and a mask layer;   forming a plurality of trenches in the substrate using the mask layers as etching masks, wherein the trenches are arranged in parallel to each other and extend in a first direction;   removing the mask layers;   forming a composite layer on the substrate covering the surface of the trenches, wherein the composite layer comprises a bottom dielectric layer, a charge-rapping layer, and a top dielectric layer; and   forming a plurality of second conductive layers on the composite layer that also fills the trenches, wherein the second conductive layers are arranged in parallel to each other and extend in a second direction and the second direction and the first direction cross over each other.   
   
   
       2 . The method of  claim 1 , wherein the step of forming the second conductive layers on the composite layer further comprises:
 forming a conductive material layer over the substrate; and   patterning the conductive material layer.   
   
   
       3 . The method of  claim 1 , wherein the material constituting the charge-trapping layer comprises silicon nitride or doped polysilicon. 
   
   
       4 . The method of  claim 1 , wherein the material constituting the bottom dielectric layer and the top dielectric layer comprises silicon oxide.