Barrier dielectric stack for seam protection

Abstract

The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

1 . A method of forming a gate structure comprising:
 forming at least one gate region atop a semiconducting substrate, said at least one gate region comprising a gate conductor atop a gate dielectric;   forming source and drain regions adjacent said at least one gate region;   forming a conformal dielectric passivation stack comprising a first conformal dielectric layer and a second conformed dielectric layer on said at least one gate region, wherein said conformal dielectric passivation stack includes a discontinuous electrical path; and   forming contacts to said source and drain regions, wherein said contacts are electrically isolated from said gate conductor by at least said conformal dielectric passivation stack.   
   
   
       2 . The method of  claim 1  wherein said forming said conformal dielectric passivation stack further comprises depositing at least one other conformal dielectric layer atop said second conformal dielectric layer, said at least one other conformal dielectric layer is seamless or having at least one other seams offset from said at least one second seam. 
   
   
       3 . The method of  claim 1  wherein said first conformal dielectric layer and said second conformal dielectric layer comprise an oxide, a nitride, or an oxynitride. 
   
   
       4 . The method of  claim 1  wherein said first conformal dielectric layer and said second conformal dielectric layer comprise the same material. 
   
   
       5 . The method of  claim 1  wherein said first conformal dielectric layer and said second conformal dielectric layer comprise a different material. 
   
   
       6 . The method of  claim 1  wherein said first conformal dielectric layer is deposited by plasma enhanced chemical vapor deposition (PECVD) and said second conformal dielectric layer is deposited using a chemical vapor deposition selected from the group consisting of atomic pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) and atomic layer deposition (ALD). 
   
   
       7 . The method of  claim 1  wherein said second conformal dielectric layer is deposited by HPCVD. 
   
   
       8 . The method of  claim 1  her comprising forming a gate silicide atop said gate conductor and a silicide contact region atop said source and drain regions.