STRAINED HOT (HYBRID OREINTATION TECHNOLOGY) MOSFETs

Abstract

A strained HOT MOSFET. The MOSFET includes (a) a first semiconductor layer having a first crystallographic orientation; (b) a buried oxide layer on top of the first semiconductor layer; (c) a second semiconductor layer on top of the buried oxide layer, wherein the second semiconductor layer has a second crystallographic orientation, and wherein the second crystallographic orientation is different from the first crystallographic orientation; (d) a third semiconductor layer on top of the first semiconductor layer, wherein the third semiconductor layer has the first crystallographic orientation; and (e) a fourth semiconductor layer on top of the third semiconductor layer, wherein the fourth semiconductor layer includes a different material than that of the third semiconductor layer, and wherein the fourth semiconductor layer has the first crystallographic orientation.

1 . A semiconductor structure, comprising:
 (a) a first semiconductor layer having a first crystallographic orientation;   (b) a buried oxide layer on top of the first semiconductor layer;   (c) a second semiconductor layer on top of the buried oxide layer, wherein the second semiconductor layer has a second crystallographic orientation, and wherein the second crystallographic orientation is different from the first crystallographic orientation;   (d) a third semiconductor layer on top of the first semiconductor layer, wherein the third semiconductor layer has the first crystallographic orientation; and   (e) a fourth semiconductor layer on top of the third semiconductor layer, wherein the fourth semiconductor layer comprises a different material than that of the third semiconductor layer, and wherein the fourth semiconductor layer has the first crystallographic orientation.   
   
   
       2 . The structure of  claim 1 , wherein the first, second, and third semiconductor layers comprise silicon, and wherein the fourth semiconductor layer comprises a mixture of Si and Ge. 
   
   
       3 . The structure of  claim 1 , wherein the first, second, and third semiconductor layers comprise silicon, and wherein the fourth semiconductor layer comprises a mixture of Si and C. 
   
   
       4 . The structure of  claim 1 , wherein the first crystallographic orientation is ( 110 ), and wherein the second crystallographic orientation is ( 100 ). 
   
   
       5 . The structure of  claim 1 , further comprising an NFET and a PFET on the second and fourth semiconductor layers, respectively.