US2008223610A1PendingUtilityA1
Bga package substrate and method of fabricating same
Est. expiryDec 30, 2024(expired)· nominal 20-yr term from priority
H10W 90/754H10W 90/734H10W 72/952H10W 72/884H10W 72/50H10W 72/29H10W 70/095H10W 90/701H10W 90/401H10W 70/685H10W 70/05H10W 70/635H05K 2201/10378H05K 2201/09509H05K 1/113H05K 2201/0394H05K 3/4623H05K 2201/09527H05K 3/4614H05K 3/46H05K 1/11
50
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.
Claims
exact text as granted — not AI-modified1 . A ball grid array package substrate, comprising:
a first external layer including a wire bonding pad; a second external layer including a solder ball pad; a first internal layer close to the first external layer; a second internal layer close to the second external layer; a first insulating layer interposed between the first external layer and the first internal layer; a second insulating layer interposed between the second external layer and the second internal layer; a third insulating layer interposed between the first internal layer and the second internal layer; a first blind via hole formed through the first insulating layer, wherein the first blind via hole is open and connected to the first internal layer through a first wall thereof at a lower side thereof and wherein the first blind via hole has a first closed portion connected to the wire bonding pad of the first external layer at an upper side thereof, the first wall being plated with a conductive material; a second blind via hole formed through the second insulating layer, wherein the second blind via hole is open and connected to the second internal layer through a second wall thereof at an upper side thereof and wherein the second blind via hole has a second closed portion connected to the solder ball pad of the second external layer at a lower side thereof, the second wall being plated with the conductive material; an upper solder resist, which is formed on the first external layer and the first insulating layer and through which a first opening is formed so as to correspond to the wire bonding pad of the first external layer; and a lower solder resist, which is formed on the second external layer and the second insulating layer and through which a second opening is formed so as to correspond to the solder ball pad of the second external layer.
2 . The ball grid array package substrate as set forth in claim 1 , wherein the wire bonding pad is formed on the first closed portion of the first blind via hole.
3 . The ball grid array package substrate as set forth in claim 1 , wherein the solder ball pad is formed on the second closed portion of the second blind via hole.
4 . The ball grid array package substrate as set forth in claim 1 , wherein the wire bonding pad is formed on the first closed portion of the first blind via hole, and the solder ball pad is formed on the second closed portion of the second blind via hole.
5 . The ball grid array package substrate as set forth in claim 1 , wherein the third insulating layer comprises at least one circuit layer having a predetermined circuit pattern.
6 - 9 . (canceled)Join the waitlist — get patent alerts
Track US2008223610A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.