Differential output circuit with reduced differential output variation

Abstract

In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.

1 - 4 . (canceled) 
   
   
       5 . A digital display comprising an interface circuit, wherein
 said interface circuit comprises a differential output circuit outputting a differential output signal from first and second output terminals and an external circuit receiving said output signal from said differential output circuit, wherein   said output circuit comprises first and second MOS transistors, first and second amplifiers, first and second loads and first, second, third, fourth and fifth switches, and said external circuit comprises an external load connected between said first and second output terminals, wherein:   said first MOS transistor has a gate connected to an output of said first amplifier, and a drain to said second and fourth switches;   said first amplifier has a negative terminal connected to a first fixed potential, and a positive terminal to said first and second loads;   said second MOS transistor has a gate connected to an output of said second amplifier, and a drain to said first and third switches;   said second amplifier has a positive terminal connected to a second fixed potential, and a negative terminal to said fifth switch at a first terminal;   said first and second switches are connected to a first node connected to said fifth switch at said first output terminal and to said first load;   said third and fourth switches are connected to a second node connected to said fifth switch at said second output terminal and to said second load;   said fifth switch has said first output terminal connected to said first terminal when said second and third switches turn on; and   said fifth switch has said second output terminal connected to said first terminal when said first and fourth switches turn on.   
   
   
       6 . The digital display device of  claim 5 , wherein the first MOS transistor is an n-channel transistor. 
   
   
       7 . The digital display device of  claim 5 , wherein the second MOS transistor is a p-channel transistor. 
   
   
       8 . The digital display device of  claim 5 , further comprising a third MOS transistor, wherein the third MOS transistor has a gate connected to a constant voltage circuit and a drain to said first and third switches. 
   
   
       9 . The digital display device of  claim 8 , wherein said third MOS transistor is a p-channel transistor. 
   
   
       10 . The digital display device of  claim 5 , further comprising an inverter circuit, wherein an output of inverter circuit is connected to said second and third switches.