Adjustment of pll bandwidth for jitter control using feedback circuitry

Abstract

Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit.

1 . A jitter control circuit for a phase lock loop circuit having an oscillator, a charge pump connected to said oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump, comprising:
 circuitry connected to the output of said oscillator to measure phase noise and control the amount of auxiliary charge pump current to manipulate the bandwidth of the PLL system and thereby reduce jitter in the phase lock loop circuit.   
   
   
       2 . The jitter control circuitry as claimed in  claim 1  wherein the circuitry connected to the oscillator and the charge pump includes circuitry to output a figure of merit which is based on the amount of phase noise produced by the said oscillator. 
   
   
       3 . The jitter control circuitry as defined in  claim 2  wherein the circuitry connected to the oscillator and the charge pump includes a state machine connected to receive the figure of merit and deliver a signal to the charge pump. 
   
   
       4 . The jitter control circuit as defined in  claim 3  wherein an analog to digital (A to D) converter is in circuit relationship to receive said figure of merit and deliver a signal to said state machine. 
   
   
       5 . The jitter control circuitry as defined in  claim 4  wherein an integrator is provided in said circuitry between said oscillator and said charge pump to deliver said figure of merit to the A to D converter. 
   
   
       6 . The jitter control circuit as defined in  claim 1  wherein a phase noise circuit is provided which supplies a measure of the phase noise. 
   
   
       7 . The phase noise measurement circuit as defined in  claim 6  wherein said phase noise measurement circuit includes a bandpass filter connected to a balanced mixer. 
   
   
       8 . The jitter control circuit as defined in  claim 7  wherein said noise measurement circuit includes an AC amplifier connected to the output of said bandpass filter. 
   
   
       9 . The jitter control circuit as defined in  claim 8  wherein a delay line is provided as input to said double balanced mixer. 
   
   
       10 . The jitter control circuit as defined in  claim 9  wherein said oscillator has a splitter attached to the output thereof, and one half of the output thereof is delivered to said delay line and the other half of the output of said oscillator is delivered to a phase shifter, and the outputs of both said delay line and said phase shifter are delivered as inputs to said double balanced mixer.