Radio frequency isolation for SOI transistors

Abstract

According to an exemplary embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby minimizing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.

1 . A structure comprising:
 at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, said buried oxide layer overlying a bulk substrate;   an electrically charged field control ring situated over said buried oxide layer and surrounding said at least one SOI transistor;   wherein said electrically charged field control ring reduces a conductivity of a surface portion of said bulk substrate underlying said field control ring, thereby minimizing RF coupling of said at least one SOI transistor through said bulk substrate.   
   
   
       2 . The structure of  claim 1  further comprising an isolation region situated between said electrically charged field control ring and said at least one SOI transistor. 
   
   
       3 . The structure of  claim 1 , wherein said electrically charged field control ring is doped with a dopant having a same conductivity type as said bulk substrate. 
   
   
       4 . The structure of  claim 1 , wherein a width of said electrically charged field control ring is greater than a thickness of said buried oxide layer. 
   
   
       5 . The structure of  claim 5 , wherein said width of said electrically charged field control ring is greater than said thickness of said buried oxide layer by a factor of between 3.0 and 10.0. 
   
   
       6 . The structure of  claim 1 , wherein said electrically charged field control ring is coupled to a bias voltage. 
   
   
       7 . The structure of  claim 1 , wherein said electrically charged field control ring comprises silicon. 
   
   
       8 . The structure of  claim 1 , wherein said electrically charged field control ring comprises a metal. 
   
   
       9 . The structure of  claim 1 , wherein said electrically charged field control ring comprises a high resistivity conductive material. 
   
   
       10 . A structure comprising:
 a plurality of SOI (semiconductor-on-insulator) transistors situated over a buried oxide, said buried oxide layer overlying a bulk substrate, said plurality of SOI transistors being coupled in series;   an electrically charged field control ring situated over said buried oxide layer and surrounding said plurality of SOI transistors;   wherein said electrically charged field control ring reduces a conductivity of a surface portion of said bulk substrate underlying said field control ring, thereby minimizing RF coupling of said plurality of SOI transistors through said bulk substrate.   
   
   
       11 . The structure of  claim 10  further comprising an isolation region situated between said electrically charged field control ring and said plurality of SOI transistors. 
   
   
       12 . The structure of  claim 10 , wherein said electrically charged field control ring is doped with a dopant having a same conductivity type as said bulk substrate. 
   
   
       13 . The structure of  claim 10 , wherein a width of said electrically charged field control ring is greater than a thickness of said buried oxide layer. 
   
   
       14 . The structure of  claim 10 , wherein said electrically charged field control ring is coupled to a bias voltage. 
   
   
       15 . The structure of  claim 10 , wherein said electrically charged field control ring comprises a conductive material selected from the group consisting of silicon and a metal. 
   
   
       16 . The structure of  claim 10 , wherein said plurality of SOI transistors form an RF switch. 
   
   
       17 . A method for minimizing RF coupling of at least one SOI transistor through a bulk substrate of an SOI substrate, said method comprising steps of:
 forming a field control ring in said SOI substrate, said field control ring surrounding said at least one SOI transistor;   electrically charging said field control ring;   wherein said field control ring reduces a conductivity of a surface portion of said bulk substrate underlying said field control ring, thereby minimizing RF coupling of said at least one SOI transistor through said bulk substrate.   
   
   
       18 . The method of  claim 17 , wherein said step of electrically charging said field control ring comprises implanting a dopant in said field control ring. 
   
   
       19 . The method of  claim 17 , wherein said step of electrically charging said field control ring comprises coupling a bias voltage to said field control ring. 
   
   
       20 . The method of  claim 17 , wherein said field control ring comprises a conductive material selected from the group consisting of silicon, polysilicon, and a metal. 
   
   
       21 . The method of  claim 17 , wherein a width of said field control ring is greater than a thickness of a buried oxide layer situated over said bulk substrate.