Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension

Abstract

A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

1 . A method for forming FET devices comprising:
 a) forming an Ultra-Thin Silicon On Insulator (UTSOI) layer atop a buried layer of insulator material region within a semiconductor substrate,   b) forming (Shallow Trench Isolation) STI regions to isolate active SOI regions for forming a respective NFET device and PFET device;   c) forming atop said active UTSOI layer a gate electrode structure for each respective NFET and PFET device in a respective isolated active UTSOI region, said gate including a gate dielectric layer formed atop said active UTSOI layer and a corresponding gate conductor formed atop said gate dielectric layer for each respective NFET and PFET device;   d) forming thin disposable spacers on each sidewall of the gate electrodes for each respective NFET and PFET device;   e) removing portions of the UTSOI layer at respective source region and drain region at each side of said gate electrode of said PFET device to create a recess at the active UTSOI region of the PFET device while leaving a thin UTSOI layer under said gate electrode defining a gate channel region for the PFET device;   f) epitaxially growing embedded semiconductor extensions in each respective recess corresponding to said source and drain regions of the PFET device;   g) depositing a layer of dielectric material over both NFET and PFET devices;   h) performing etching of said dielectric layer to form thick disposable gate sidewall spacers at both NFET and PFET devices;   i) forming raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions of the PFET device and, forming raised source/drain (RSD) structures on top of said UTSOI layer at respective source region and drain region at each side of said gate electrode of said NFET device; and,   j) removing said thick SiN disposable sidewall spacers at both NFET and PFET devices,   wherein said epitaxially grown embedded semiconductor extensions create compressive stress in the UTSOI channel layer of said PFET device thereby enhancing device performance.   
   
   
       2 . The method as claimed in  claim 1 , wherein said STI forming step b) comprises:
 forming STI trenches using lithographic processes; and,   depositing an STI dielectric material in the formed trenches, annealing and chemical mechanical polishing (CMP) the resultant structure.   
   
   
       3 . The method as claimed in  claim 2 , wherein said STI dielectric material is one of an oxide, nitride or oxynitride material. 
   
   
       4 . The method as claimed in  claim 1 , wherein a thickness of said UTSOI layer ranges between 10 Å to about 300 Å. 
   
   
       5 . The method as claimed in  claim 1 , further comprising forming respective p-well and n-well structures in respective UTSOI regions for respective NFET and PFET devices. 
   
   
       6 . The method as claimed in  claim 2 , wherein prior to forming disposable spacers at step d), the steps of:
 forming a capping layer for each respective NFET and PFET gate structure comprising a dielectric capping material; and,   forming a re-oxidized (ReOx) thin layer of material to cover each gate and respective active region for each NFET and PFET device.   
   
   
       7 . The method as claimed in  claim 6 , wherein said step d) of forming thin disposable spacers comprises:
 blanket depositing a thin conformal layer of dielectric material by a chemical vapor deposition (CVD) process over each of the respective devices;   covering only the NFET device with a resist material;   performing a reactive ion etch (RE) on the PFET device to form the thin disposable spacers on said PFET device,   wherein said thin conformal layer of dielectric material is removed from atop the ReOx layer at the PFET device as a result of said RIE.   
   
   
       8 . The method as claimed in  claim 1 , wherein said epitaxially grown embedded extensions include a Si-containing material. 
   
   
       9 . The method as claimed in  claim 8 , wherein said Si-containing material comprises SiGe material. 
   
   
       10 . The method as claimed in  claim 1 , wherein said step g) of depositing a dielectric material includes depositing an SiN material by LPCVD. 
   
   
       11 . The method as claimed in  claim 1 , wherein said step j) of removing said thick disposable sidewall spacers comprises performing a RIE. 
   
   
       12 . The method as claimed in  claim 1 , wherein said step i) of forming RSD includes epitaxially growing said raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions. 
   
   
       13 . The method as claimed in  claim 12 , wherein said epitaxially grown raised source/drain (RSD) structures comprise a Si-containing material. 
   
   
       14 . A semiconductor transistor device comprising:
 a semiconductor substrate having a buried layer of insulator material formed therein and an Ultra-thin Silicon On Insulator (UTSOI) layer formed a top said buried layer of insulator material;   STI (Shallow Trench Isolation) structures formed in said UTSOI layer for isolating active areas for forming an NFET device and PFET for forming a gate channel region for respective NFET and PFET device;   a gate structure including a gate dielectric layer formed in each isolated active area for each respective NFET and PFET device and a gate electrode conductor formed atop each said respective gate dielectric layer for each respective NFET and PFET device;   epitaxially grown embedded semiconductor extensions formed in respective recesses created as a result of removing portions of the SOI layer at respective source region and drain region at each side of said gate electrode of said PFET device;   raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions corresponding to said source and drain regions of the PFET device; and,   raised source/drain (RSD) structures on top of source and drain regions of the NFET device,   wherein said epitaxially grown embedded semiconductor extensions create compressive stress in the UTSOI layer thereby enhancing PFET device performance.   
   
   
       15 . The semiconductor transistor device as claimed in  claim 14 , wherein said formed eSiGe extensions abut the short SOI channel region to maximize its compressive stress effect. 
   
   
       16 . The semiconductor transistor device as claimed in  claim 14 , wherein said formed epitaxial raised source/drain (RSD) structures range between 100 to 400 angstroms in thickness for said PFET device. 
   
   
       17 . The semiconductor transistor device as claimed in  claim 14 , wherein, for each formed NFET and PFET device, each said formed epitaxial RSD structures are located a distance from an edge of a respective gate conductor that is sufficient to lower parasitic capacitance between the gate and the respective source/drain structure for each formed NFET and PFET device. 
   
   
       18 . The semiconductor transistor device as claimed in  claim 14 , wherein said distance between between each formed RSD structure and a respective gate edge is between 30 nm-40 nm. 
   
   
       19 . A semiconductor transistor device comprising:
 a semiconductor substrate having a buried layer of insulator material formed therein and an Ultra-thin Silicon On Insulator (UTSOI) layer formed a top said buried layer of insulator material, said UTSOI layer providing an active area for a PFET device;   a gate structure including a gate dielectric layer formed in said UTSOI active area for said PFET device and a gate electrode conductor formed atop said gate dielectric layer;   epitaxially grown embedded semiconductor extensions formed in respective recesses created as a result of removing portions of the UTSOI layer at respective source region and drain region at each side of said gate structure of said PFET device; and,   raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions,   wherein said epitaxially grown embedded semiconductor PFET extensions create compressive stress in the UTSOI layer thereby enhancing PFET device performance.   
   
   
       20 . A method for forming FET devices comprising:
 a) forming an Ultra-thin Silicon On Insulator (UTSOI) layer a top a buried layer of insulator material within a semiconductor substrate, said UTSOI layer providing an active area for a PFET device;   b) forming atop said UTSOI active area a gate structure for said PFET device, said gate structure including a gate dielectric layer formed atop said UTSOI active layer and a corresponding gate conductor formed atop said gate dielectric layer;   c) removing portions of the UTSOI layer at respective source region and drain region at each side of said gate electrode of said PFET device to create a respective recess at the active UTSOI area while leaving said UTSOI layer under said gate electrode defining a gate channel region for the PFET device;   d) epitaxially growing embedded semiconductor extensions in each respective recess corresponding to said source and drain regions of the PFET device; and   e) forming thick disposable sidewall spacers at sidewalls of said gate electrode of said PFET device;   f) forming raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions corresponding to said source and drain regions of the PFET device; and,   g) removing said thick disposable sidewall spacers at said PFET device,   wherein said epitaxially grown embedded semiconductor extensions create compressive stress in the thin SOI layer thereby enhancing device performance.