Pixel for CMOS Image Sensor Having a Select Shape for Low Pixel Crosstalk

Abstract

A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an array of pixels.

1 . An array, comprising:
 a plurality of pixels,   each pixel comprising:   a substantially square image sensing region, wherein a first distance along a first axis is substantially the same as a second distance along a second axis that is orthogonal to the first axis, wherein the first and the second distances are distances between image sensing regions of neighboring pixels; and   a substantially hemispherical microlens positioned over the image sensing region of each pixel.   
     
     
         2 . The array of  claim 1 , wherein the difference between the first and second distances is no more than 0.2 micrometer. 
     
     
         3 . The array of  claim 1 , wherein the position of the substantially hemispherical microlens is configured to increase an effective fill factor. 
     
     
         4 . The array of  claim 1 , wherein the pixel further comprises:
 a transfer transistor having a first source-drain region coupled to the image sensing region, a gate controlled by a first control signal and a second source-drain region coupled to a floating sensing node;   a reset transistor having a third source-drain region coupled to a reset potential, a gate controlled by a second control signal and a fourth source-drain region coupled to the floating sensing node; and   a source follower coupled between the floating sensing node and an output of the pixel, the source follower controlled by a select signal.   
     
     
         5 . The array of  claim 4 , wherein the transfer transistor, the reset transistor, and the source follower are positioned along at least two sides of the pixel. 
     
     
         6 . The array of  claim 4 , wherein the reset transistor is a depletion mode transistor. 
     
     
         7 . The array of  claim 4 , wherein the source follower comprises:
 a first transistor having a first source-drain region coupled to a voltage supply, a gate coupled to the floating sensing node, and a second source-drain region coupled to a first source-drain region of a second transistor; and   the second transistor having a second source-drain region coupled to the output of the pixel and a gate receiving the select signal.   
     
     
         8 . An array, comprising:
 a plurality of pixels, each pixel defining a substantially square area;   a plurality of substantially square image sensing regions, each sensing region defined within a corresponding pixel; and   a plurality of substantially hemispherical microlenses, each positioned over a corresponding square image sensing region.   
     
     
         9 . The array of  claim 8 , wherein the square image sensing region defines a first distance along a first axis and a second distance along a second axis that is orthogonal to the first axis, wherein the first distance is substantially the same as the second distance and the first and the second distances are distances between image sensing regions of neighboring pixels. 
     
     
         10 . The array of  claim 9 , wherein the difference between the first and second distance is no more than 0.2 micrometer. 
     
     
         11 . The array of  claim 8 , wherein the position of the substantially hemispherical microlens is configured to increase an effective fill factor. 
     
     
         12 . The array of  claim 8 , wherein the pixel further comprises:
 a transfer transistor having a first source-drain region coupled to the image sensing region, a gate controlled by a first control signal and a second source-drain region coupled to a floating sensing node;   a reset transistor having a third source-drain region coupled to a reset potential, a gate controlled by a second control signal and a fourth source-drain region coupled to the floating sensing node; and   a source follower coupled between the floating sensing node and an output of the pixel, the source follower controlled by a select signal.   
     
     
         13 . The array of  claim 12 , wherein the transfer transistor, the reset transistor, and the source follower are positioned along at least two sides of the pixel. 
     
     
         14 . The array of  claim 12 , wherein the reset transistor is a depletion mode transistor. 
     
     
         15 . The array of  claim 12 , wherein the source follower comprises:
 a first transistor having a first source-drain region coupled to a voltage supply, a gate coupled to the floating sensing node, and a second source-drain region coupled to a first source-drain region of a second transistor; and   the second transistor having a second source-drain region coupled to the output of the pixel and a gate receiving the select signal.