Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor

Abstract

A simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again.

1 . A processor comprising:
 a first multiplexer to receive a first instruction thread;   a second multiplexer to receive a second instruction thread;   a first storage element to store a set of instruction pointers associated with the first instruction thread from the first multiplexer if the first thread is inactive;   a second storage element to store a set of instruction pointers associated with the second instruction thread from the second multiplexer if the second thread is inactive;   a first inactive thread re-steer logic to cause the first multiplexer to receive the first thread if the first thread becomes active;   a second inactive thread re-steer logic to cause the second multiplexer to receive the second thread if the second thread becomes active.   
   
   
       2 . The processor of  claim 1 , further comprising a common multiplexer coupled between said first and second multiplexer. 
   
   
       3 . The processor of  claim 2 , wherein the common multiplexer is to receive instruction pointer information sequentially from the first multiplexer and the second multiplexer in a time-multiplexed manner. 
   
   
       4 . The processor of  claim 2 , wherein the common multiplexer is to receive instruction pointer information sequentially from the first multiplexer and the second multiplexer in an alternating manner. 
   
   
       5 . The processor of  claim 1 , wherein the first multiplexer and the second multiplexer are priority multiplexers. 
   
   
       6 . The processor of  claim 5 , wherein the first multiplexer and the second multiplexer are to receive instruction pointer information and data from a plurality of stages in a processor pipeline. 
   
   
       7 . The processor of  claim 6 , wherein the first multiplexer and the second multiplexer are to receive instruction pointer information and data from re-steer logic at the plurality of stages in the processor pipeline. 
   
   
       8 . The processor of  claim 7 , wherein the first multiplexer and the second multiplexer are to pass the instruction pointer information and data to a common multiplexer along with a priority indicator. 
   
   
       9 . The processor of  claim 1 , wherein the storage element is a flip-flop device.