SDRAM with Reset Function

Abstract

A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes a low voltage MOS input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRS P which indicates a time when a mode register is to be loaded with data. The reset circuit activates the Reset_En signal in response to the external Reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the SDRAM IC are powered down.

1 . A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC, the SDRAM IC comprising:
 a low voltage CMOS input buffer configured to generate a buffered reset signal RST from the external Reset signal; and   a reset circuit configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRS P  which indicates a time when a mode register is to be loaded with data,   wherein the reset circuit activates the Reset_En signal in response to the external Reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the SDRAM IC are powered down.   
   
   
       2 . The SDRAM IC of  claim 1  wherein a duration of the internal reset interval is dependent on when the CKE signal becomes active to indicate that the SDRAM is ready to receive an external command. 
   
   
       3 . The SDRAM IC of  claim 1  wherein a duration of the internal reset interval is dependent on when the CKE signal becomes active to indicate SDRAM internal initialization is completed. 
   
   
       4 . The SDRAM IC of  claim 1  wherein the reset circuit comprises a delay circuit configured so that a duration of the internal reset interval is in part dependent upon the propagation delay through the delay circuit. 
   
   
       5 . The SDRAM IC of  claim 4  wherein an input of the delay circuit is coupled to the CKE signal. 
   
   
       6 . The SDRAM IC of  claim 4  wherein the delay circuit is an inverting delay circuit. 
   
   
       7 . The SDRAM IC of  claim 1  wherein the reset circuit further comprises a latch circuit configured to prevent the Reset_En signal from changing states when CKE signal makes transitions during predetermined timing periods. 
   
   
       8 . The SDRAM IC of  claim 1  wherein the reset circuit further comprises a latch circuit configured to render the Reset_En signal non-responsive to CKE signal transitions during the time the external Reset signal is in inactive state. 
   
   
       9 . The SDRAM IC of  claim 1  wherein the reset circuit further comprises a pull-up circuit configured to bias the latch circuit in a first state in response the MRS P  signal becoming active, the first state of the latch circuit rendering the Reset_En signal non-responsive to CKE signal transitions during the time the external Reset signal is in inactive state. 
   
   
       10 . The SDRAM IC of  claim 1  wherein the input buffer comprises a two-input logic gate having one input coupled to a supply voltage and the other input coupled to the external Reset signal. 
   
   
       11 . The SDRAM IC of  claim 1  wherein the reset circuit comprises:
 a first two-input NAND gate providing the Reset_En signal at its output and receiving the RST signal at a first input;   a second two-input NAND gate having an output coupled to a second input of the first two-input NAND gate, the second two-input NAND gate having a first input coupled to a clock enable signal CKE through an inverting delay circuit;   a two-input NOR gate receiving the RST signal at a first input and the CKE signal at a second input;   a pull-up transistor and a pull-down transistor serially coupled between a supply voltage and a ground potential, the pull-down transistor having a gate terminal coupled to an output of the two-input NOR gate;   an inverter having its input coupled to the MRS P  signal and its output coupled to a gate terminal of the pull-up transistor; and   a latch circuit coupled between a second input of the second two-input NAND gate and a node intermediate serially connected pull-up and pull-down transistors.   
   
   
       12 . The SDRAM IC of  claim 11  wherein the latch circuit comprises two cross-coupled inverters.