Method of assembling chips

Abstract

A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

1 - 20 . (canceled) 
     
     
         21 . A chip package comprising:
 a first substrate;   a chip over said first substrate;   a copper pillar between said chip and said first substrate, wherein said copper pillar has a thickness greater than a vertical distance between said copper pillar and said first substrate; and   a tin-containing layer between said copper pillar and said first substrate and on a sidewall of said copper pillar.   
     
     
         22 . The chip package of  claim 21 , wherein said tin-containing layer comprises silver. 
     
     
         23 . The chip package of  claim 21 , wherein said tin-containing layer comprises lead. 
     
     
         24 . The chip package of  claim 21 , wherein said copper pillar is between a pad of said chip and said first substrate, wherein said copper pillar is connected to said pad, and wherein said copper pillar has a transverse dimension less than that of said pad. 
     
     
         25 . The chip package of  claim 21  further comprising an encapsulating material between said chip and said first substrate, wherein said encapsulating material contacts with said chip and said first substrate. 
     
     
         26 . The chip package of  claim 21  further comprising a second substrate and a metal bump between said chip and said second substrate. 
     
     
         27 . The chip package of  claim 26  further comprising a solder ball under said second substrate, wherein said solder ball is connected to said second substrate, and wherein said chip is over said second substrate. 
     
     
         28 . The chip package of  claim 21 , wherein said first substrate comprises a ceramic substrate. 
     
     
         29 . A chip package comprising:
 a first substrate;   a chip over said first substrate;   a copper pillar between said chip and said first substrate, wherein said copper pillar has a thickness greater than a vertical distance between said copper pillar and said first substrate;   a tin-and-gold-containing layer between said copper pillar and said first substrate, wherein said thickness of said copper pillar is greater than that of said tin-and-gold-containing layer; and   a tin-containing layer on a sidewall of said copper pillar.   
     
     
         30 . The chip package of  claim 29 , wherein said tin-containing layer comprises silver. 
     
     
         31 . The chip package of  claim 29 , wherein said tin-containing layer comprises lead. 
     
     
         32 . The chip package of  claim 29 , wherein said copper pillar is between a pad of said chip and said first substrate, wherein said copper pillar is connected to said pad, and wherein said copper pillar has a transverse dimension less than that of said pad. 
     
     
         33 . The chip package of  claim 29  further comprising an encapsulating material between said chip and said first substrate, wherein said encapsulating material contacts with said chip and said first substrate. 
     
     
         34 . The chip package of  claim 29  further comprising a second substrate and a metal bump between said chip and said second substrate. 
     
     
         35 . The chip package of  claim 34  further comprising a solder ball under said second substrate, wherein said solder ball is connected to said second substrate, and wherein said chip is over said second substrate. 
     
     
         36 . The chip package of  claim 29 , wherein said first substrate comprises a ceramic substrate. 
     
     
         37 . A chip package comprising:
 a substrate;   a chip over said substrate;   a copper pillar between said chip and said substrate, wherein said copper pillar has a thickness greater than a vertical distance between said copper pillar and said substrate; and   a tin-containing layer between said chip and said substrate, wherein said tin-containing layer covers a bottom surface of said copper pillar and a sidewall of said copper pillar.   
     
     
         38 . The chip package of  claim 37 , wherein said tin-containing layer comprises silver. 
     
     
         39 . The chip package of  claim 37 , wherein said tin-containing layer comprises lead. 
     
     
         40 . The chip package of  claim 37 , wherein said copper pillar is between a pad of said chip and said substrate, wherein said copper pillar is connected to said pad, and wherein said copper pillar has a transverse dimension less than that of said pad.