Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit

Abstract

Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

1 . A method of forming a magnetic tunnel junction, the method comprising the steps of:
 forming a film stack, the film stack comprising one or more magnetic layers;   forming one or more trenches in the film stack, sidewalls of the one or more trenches being substantially vertical;   forming a spacer layer at least partially on top of the film stack;   etching the spacer layer such that portions of the spacer layer only remain on the sidewalls of the one or more trenches in the film stack; and   etching at least a portion of the film stack utilizing the etched spacer layer as a mask.   
   
   
       2 . The method of  claim 1 , wherein at least one of the one or more magnetic layers comprises a ferromagnetic material. 
   
   
       3 . The method of  claim 1 , wherein the film stack comprises at least one of cobalt, nickel, iron, and a combination thereof. 
   
   
       4 . The method of  claim 1 , wherein the film stack comprises one or more masking layers, portions of the one or more masking layers acting as a mask during the step of etching at least a portion of the film stack. 
   
   
       5 . The method of  claim 3 , wherein at least one of the one or more masking layers comprises a refractory material. 
   
   
       6 . The method of  claim 1 , wherein the step of forming the one or more trenches in the film stack is performed using photolithography. 
   
   
       7 . The method of  claim 1 , wherein the spacer layer comprises a dielectric material. 
   
   
       8 . The method of  claim 1 , wherein the spacer layer comprises an electrically conductive material. 
   
   
       9 . The method of  claim 1  wherein the spacer layer comprises tantalum nitride or titanium nitride. 
   
   
       10 . The method of  claim 1  wherein the step of depositing the spacer layer is performed using chemical vapor deposition. 
   
   
       11 . The method of  claim 1 , wherein the step of etching the spacer layer is performed using substantially anisotropic etching. 
   
   
       12 . The method of  claim 1 , wherein the step of etching the spacer layer is performed using reactive ion etching. 
   
   
       13 . The method of  claim 1 , wherein the step of etching at least a portion of the film stack utilizing the etched spacer layer as a mask is performed using substantially anisotropic etching. 
   
   
       14 . The method of  claim 1 , wherein the step of etching at least a portion of the film stack utilizing the etched spacer layer as a mask comprises using reactive ion etching. 
   
   
       15 . The method of  claim 1 , further comprising the step of wet chemical etching at least a portion of the film stack with the etched spacer layer in place. 
   
   
       16 . The method of  claim 1 , further comprising the step of thermally oxidizing at least a portion of the film stack with the etched spacer layer in place. 
   
   
       17 . The method of  claim 1 , further comprising forming a metallization feature above at least a portion of the film stack, wherein the etched spacer layer is operative to electrically connect the film stack to the metallization feature. 
   
   
       18 . A semiconductor wafer comprising a plurality of integrated circuits, the plurality of integrated circuits comprising one or more magnetic tunnel junctions formed at least in part by the steps of:
 forming a film stack, the film stack comprising one or more magnetic layers;   forming one or more trenches in the film stack, sidewalls of the one or more trenches being substantially vertical;   forming a spacer layer at least partially on top of the film stack;   etching the spacer layer such that portions of the spacer layer only remain on the sidewalls of the one or more trenches in the film stack; and   etching at least a portion of the film stack utilizing the etched spacer layer as a mask.   
   
   
       19 . An integrated circuit comprising one or more magnetic tunnel junctions, the one or more magnetic tunnel junctions formed at least in part by the steps of:
 forming a film stack, the film stack comprising one or more magnetic layers;   forming one or more trenches in the film stack, sidewalls of the one or more trenches being substantially vertical;   forming a spacer layer at least partially on top of the film stack;   etching the spacer layer such that portions of the spacer layer only remain on the sidewalls of the one or more trenches in the film stack; and   etching at least a portion of the film stack utilizing the etched spacer layer as a mask.   
   
   
       20 . The integrated circuit of  claim 19 , wherein the integrated circuit comprises magnetic random access memory circuitry.