Semiconductor device

Abstract

A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G 1 , a source lead S 1 , and a drain lead D 2 are arranged from left to right on the first surface of the package and a drain lead D 1 , a source lead S 2 , and a gate lead G 2 are arranged from left to right on the second surface. A gap between the source lead S 1 and the drain lead D 2 is two times a gap between the gate lead G 1 and the source lead S 1 , and a gap between the drain lead D 1 and the source lead S 2 is two times a gap between the source lead S 2 and the gate lead G 2.

1 . A semiconductor device comprising:
 a first semiconductor chip including a N-channel type MISFET and having a first gate electrode, a first source electrode and a first drain electrode,   a second semiconductor chip including a N-channel type MISFET and having a second gate electrode, a second source electrode and a second drain electrode,   a first gate lead, a first source lead and a first drain lead electrically connected to the first gate electrode, the first source electrode and the first drain electrode, respectively, the first gate lead, the first source lead and the first drain lead having a first gate lead terminal, a first source lead terminal and a first drain lead terminal, respectively;   a second gate lead, a second source lead and a second drain lead electrically connected to the second gate electrode, the second source electrode and the second drain electrode, respectively, the second gate lead, the second source lead and the second drain lead having a second gate lead terminal, a second source lead terminal and a second drain lead terminal, respectively; and   an insulating resin covering the first and second semiconductor chips and parts of the first gate lead, the first source lead, the first drain lead, the second gate lead, the second source lead and the second drain lead, the insulating resin having a first side surface and a second side surface opposite to the first side surface,   wherein the first gate lead terminal, the first source lead terminal and the second drain lead terminal protrude from the first side surface of the insulating resin,   wherein the first source lead terminal is positioned between the first gate lead terminal and the second drain lead terminal,   wherein the first drain lead terminal, the second source lead terminal and the second gate lead terminal protrude from the second side surface of the insulating resin,   wherein the second source lead terminal is positioned between the first drain lead terminal and the second gate lead terminal,   wherein a first distance between the second drain lead terminal and the first source lead terminal is greater than a second distance between the first source lead terminal and the first gate lead terminal, and   wherein a third distance between the first drain lead terminal and the second source lead terminal is greater than a fourth distance between the second source lead terminal and the second gate lead terminal.   
     
     
         2 . A semiconductor device according to  claim 1 , wherein each of the first and second semiconductor chips has a top surface and a bottom surface opposite to the top surface,
 wherein the first gate electrode and first source electrode are disposed on the top surface of the first semiconductor chip;   wherein the first drain electrode is disposed on the bottom surface of the first semiconductor chip,   wherein the second gate electrode and second source electrode are disposed on the top surface of the second semiconductor chip, and   wherein the second drain electrode is disposed on the bottom surface of the second semiconductor chip.   
     
     
         3 . A semiconductor device according to  claim 1 , wherein the first gate electrode and the first gate lead are electrically connected via a first gate wire,
 wherein the first source electrode and the first source lead are electrically connected via a first source wire,   wherein the second gate electrode and the second gate lead are electrically connected via a second gate wire, and   wherein the second source electrode and the second source lead are electrically connected via a second source wire.   
     
     
         4 . A semiconductor device according to  claim 1 , wherein the first lead includes a first chip mounting portion disposed inside the insulating resin,
 wherein the second lead includes a second chip mounting portion disposed inside the insulating resin,   wherein the first semiconductor chip is mounted on the first chip mounting portion, and   wherein the second semiconductor chip is mounted on the second chip mounting portion.   
     
     
         5 . A semiconductor device according to  claim 1 , wherein the N-channel type MISFET and the P-channel type MISFET are vertical type power MOSFETs 
     
     
         6 . A semiconductor device according to  claim 1 , wherein the N-channel type MISFET has a breakdown voltage of 600 V. 
     
     
         7 . A semiconductor device according to  claim 1 , wherein the P-channel type MISFET has a breakdown voltage of 600 V.