Semiconductor Device Having an Implanted Precipitate Region and a Method of Manufacture Therefor

Abstract

The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device 100 , among other things, may include a substrate 110 having a lattice structure and having an implanted precipitate region 120 located within the lattice structure. Additionally, the semiconductor device 100 may include a dynamic defect 125 located within the lattice structure and proximate the implanted precipitate region 120 , such that the implanted precipitate region 120 affects a position of the dynamic defect 125 within the lattice structure. Located over the substrate 110 in the aforementioned semiconductor device 100 is a gate structure 160.

1 . A semiconductor device, comprising:
 a substrate having a lattice structure and having an implanted precipitate region located within said lattice structure;   a dynamic defect located within said lattice structure and proximate said implanted precipitate region, such that said implanted precipitate region affects a position of said dynamic defect within said lattice structure; and   a gate structure located over said substrate.   
   
   
       2 . The semiconductor device as recited in  claim 1  wherein said implanted precipitate region comprises a SiO 2  precipitate region. 
   
   
       3 . The semiconductor device as recited in  claim 1  wherein said implanted precipitate region comprises a SiN precipitate region. 
   
   
       4 . The semiconductor device as recited in  claim 1  wherein said implanted precipitate region is located from about 60 nm to about 150 nm below said gate structure. 
   
   
       5 . The semiconductor device as recited in  claim 1  wherein said implanted precipitate region is noncontinuous. 
   
   
       6 . The semiconductor device as recited in  claim 1  wherein said dynamic defect is an edge dislocation, a vacancy, a dislocation loop formed by an agglomeration of vacancies within said lattice, a silicon self-interstitial atom, a substitutional atom, or a dislocation loop formed by the agglomeration of self interstitial atoms. 
   
   
       7 . The semiconductor device as recited in  claim 1  wherein said substrate is a first silicon substrate and said device further includes a silicon-germanium layer located over said first silicon substrate and a second silicon substrate located over said silicon-germanium layer, wherein said silicon-germanium layer is in a relaxed state and said second silicon substrate is in a stressed state. 
   
   
       8 . The semiconductor device as recited in  claim 1  wherein said substrate is a first silicon substrate and said device further includes an implanted silicon-germanium region within said first silicon region and a second silicon substrate located over said first silicon substrate, wherein said second silicon substrate is in a stressed state. 
   
   
       9 . The semiconductor device as recited in  claim 1  wherein said substrate is a first silicon substrate and said device further includes a silicon or germanium implant induced dynamic defect region within said first silicon region wherein said first silicon substrate is in a stressed state induced by said silicon or germanium implant induced dynamic defect region. 
   
   
       10 - 22 . (canceled) 
   
   
       23 . An integrated circuit, comprising:
 a substrate having a lattice structure and having an implanted precipitate region located within said lattice structure;   a dynamic defect located within said lattice structure and proximate said implanted precipitate region, such that said implanted precipitate region affects a position of said dynamic defect within said lattice structure;   transistors located over said substrate; and   interconnects connecting said transistors to form an operational integrated circuit.   
   
   
       24 . The integrated circuit as recited in  claim 23  wherein said implanted precipitate region comprises a SiO 2  precipitate region. 
   
   
       25 . The integrated circuit as recited in  claim 23  wherein said implanted precipitate region comprises a SiN precipitate region. 
   
   
       26 . The integrated circuit as recited in  claim 23  wherein said implanted precipitate region is located from about 60 nm to about 150 nm below said gate structure. 
   
   
       27 . The integrated circuit as recited in  claim 23  wherein said substrate is a first silicon substrate and said device further includes a silicon-germanium layer located over said first silicon substrate and a second silicon substrate located over said silicon-germanium layer, wherein said silicon-germanium layer is in a relaxed state and said second silicon substrate is in a stressed state. 
   
   
       28 . The integrated circuit as recited in  claim 23  wherein said substrate is a first silicon substrate and said device further includes a silicon or germanium implant induced dynamic defect region within said first silicon region wherein said first silicon substrate is in a stressed state induced by said silicon or germanium implant induced dynamic defect region.