Storage nodes and methods of manufacturing and operating the same, phase change memory devices and methods of manufacturing and operating the same

Abstract

In various embodiments, the present disclosure may provide a storage node. In various implementations, the storage node may include a bottom electrode having a non-planar bottom surface that conforms with and is connected to a non-planar top surface of a diode electrode of a memory device. The storage node may further include a phase change layer on top of a bottom diode and a top electrode on a top surface of a phase change layer.

1 . A storage node, comprising:
 a bottom electrode having a non-planar bottom surface that is connected to a switching device of a memory device;   a phase change layer on top of the bottom electrode; and   a top electrode on a top surface of the phase change layer.   
     
     
         2 . The storage node of  claim 1 , wherein a bottom surface of the bottom electrode is concave or upwardly convex. 
     
     
         3 . The storage node of  claim 1 , wherein further comprising a spacer surrounding the bottom electrode and at least portion of the phase change layer. 
     
     
         4 . The storage node of  claim 1 , wherein the bottom electrode is formed of a compound including at least one of titanium (Ti) and a nitride (N). 
     
     
         5 . The storage node of  claim 4 , wherein the bottom electrode is formed of one of titanium nitride (TiN) and titanium aluminum nitride (TiAlN). 
     
     
         6 . A phase change memory device comprising:
 a switching device formed on a semiconductor substrate; and   the storage node of  claim 1  connected to the switching device.   
     
     
         7 . The phase change memory device of  claim 6  further comprising:
 a first insulating interlayer having a hole having at least portion of the storage node therewithin;   a diode filling a lower region of the hole; and   the diode electrode on the diode.   
     
     
         8 . The phase change memory device of  claim 7 , further comprising a spacer annularly disposed along a sidewall of the hole between the sidewall and the phase change layer. 
     
     
         9 . The phase change memory device of  claim 7 , wherein an interface connecting the diode electrode with the bottom electrode is concave or upwardly convex. 
     
     
         10 . The phase change memory device of  claim 7 , wherein the diode electrode includes silicon (Si). 
     
     
         11 . The phase change memory device of  claim 10 , wherein the diode electrode includes metal silicide. 
     
     
         12 . The phase change memory device of  claim 11 , wherein the diode electrode is formed of at least one of TiSi 2 , CoSi 2 , and NiSi 2 . 
     
     
         13 . The phase change memory device of  claim 7 , wherein an area of a top surface of the diode electrode is equal to an area of a bottom surface of the bottom electrode. 
     
     
         14 . A method of manufacturing a phase change memory device, the method comprising:
 forming an insulating interlayer on a semiconductor substrate;   forming a hole in the insulating interlayer to expose the semiconductor substrate;   forming a diode in a lower region of the hole;   forming a diode electrode on the diode so that an exposed surface of the diode electrode is non-planar;   forming a bottom electrode in contact with and conforming to the non-planar surface of the diode electrode; and   sequentially forming a phase change layer and a top electrode on the bottom electrode.   
     
     
         15 . The method of  claim 14 , wherein the forming the diode comprises:
 filling the lower region of the hole with a semiconductor layer;   doping a lower region of the semiconductor layer with a first conductive impurity; and   doping an upper region of the semiconductor layer with a second conductive impurity.   
     
     
         16 . The method of  claim 15 , wherein the filling the lower region of the hole with the semiconductor layer comprises:
 filling the hole with a single crystal semiconductor layer using a selective epitaxial growth method;   planarizing a top surface of the single crystal semiconductor layer until a top surface of the first insulating interlayer is exposed; and   removing a part of the planarized single crystal semiconductor layer from the hole.   
     
     
         17 . The method of  claim 14 , wherein the forming the diode electrode comprises:
 forming an annular spacer so that the spacer contacts the diode and covers a sidewall of the hole;   forming a recess in a top surface of the diode inside the spacer; and   covering a surface of the recess with a conductive layer.   
     
     
         18 . The method of  claim 14 , wherein the diode electrode includes silicon. 
     
     
         19 . The method of  claim 18 , wherein the diode electrode is formed of metal silicide. 
     
     
         20 . The method of  claim 19 , wherein the metal silicide comprises at least one of TiSi 2 , CoSi 2 , and NiSi 2 . 
     
     
         21 . The method of  claim 14 , wherein sequentially forming the phase change layer and the top electrode comprises:
 filling the hole and covering a top surface of the insulating interlayer with the phase change layer;   forming the top electrode on a top surface of the phase change layer; and   etching a portion of the top diode and the phase change layer to expose a top surface of the insulating interlayer.   
     
     
         22 . The method of  claim 21 , wherein etching a portion of the top electrode and the phase change layer comprises:
 forming a photosensitive layer pattern on a top surface of the top electrode;   etching the of the top electrode and the phase change layer around the photosensitive layer pattern to define a storage node region of the phase change memory device; and   removing the photosensitive layer pattern to expose the storage node region.   
     
     
         23 . The method of  claim 14 , wherein the sequentially forming the phase change layer and the top electrode comprises:
 filling the hole to a top surface of the insulating interlayer with the phase change layer;   forming the top electrode on top surfaces of the phase change layer and the insulating interlayer; and   etching a portion of the top electrode to expose a top surface of the insulating interlayer.   
     
     
         24 . A method of operating a phase change memory device, the method comprising:
 applying an operating voltage to a storage node of a phase change memory device, the applied voltage inducing a current flow through the storage node and a non-planar interface between the storage node and a diode electrode connecting a diode with the storage node, the induced current turning the diode on.   
     
     
         25 . The method of  claim 24 , wherein the operating voltage is one of:
 a write voltage for inducing a current to store data on the storage node;   a read voltage for inducing a current to read data stored on the storage node; and   an erase voltage for inducing a current to erase data stored on the storage node.