US2008209722A1PendingUtilityA1

Method for forming via hole having fine hole land

Assignee: SAMSUNG ELECTRO MECHPriority: Dec 12, 2005Filed: Feb 6, 2008Published: Sep 4, 2008
Est. expiryDec 12, 2025(expired)· nominal 20-yr term from priority
Y10T29/49165H05K 3/428H05K 2203/0542Y10T29/49155H05K 3/40H05K 3/064H05K 2201/09545Y10T29/49128H05K 2203/1394
48
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Claims

Abstract

A method for forming a via hole having a fine hole land with which the density of circuit patterns can be increased. The method includes forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.

Claims

exact text as granted — not AI-modified
1 . A method for forming a via hole having a fine hole land, comprising:
 (a) forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate;   (b) forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and   (c) forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.   
   
   
       2 . The method as set forth in  claim 1 , wherein operation (a) comprises;
 forming the via hole in the copper clad laminate using a drilling process;   coating an etching resist in a circuit pattern over the copper clad laminate in a circuit pattern; and   forming a circuit pattern using an exposure process.   
   
   
       3 . The method as set forth in  claim 1 , wherein operation (b) comprises:
 forming the seed layer using an electroless plating process and an electroplating process;   layering the photoresist on the seed layer; and   exposing the inner wall of the via hole through an exposure and development process with the photoresist serving as a mask.   
   
   
       4 . The method as set forth in  claim 3 , wherein the seed layer is 1.5 μm thick. 
   
   
       5 . The method as set forth in  claim 1 , wherein operation (c) comprises:
 forming a copper layer on the inner wall of the via hole with the seed layer serving as a plating bar;   removing the photoresist; and   removing the seed layer by flash etching.   
   
   
       6 . The method as set forth in  claim 5 , wherein the copper layer has a thickness of 15 μm or greater. 
   
   
       7 . The method as set forth in  claim 1 , further comprising operation (d) of exposing a circumference of the via hole, wherein the circumference of the via hole is plated upon the formation of the plated layer on the inner wall of the via hole in operation (c).

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