Processor and compiler for decoding an instruction and executing the instruction with conditional execution flags

Abstract

The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C 6 ,C 1 :C 4 ,TAR,Ra”, the processor (i) sets a conditional flag C 4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C 2 to a conditional flag C 1 , moves the value of a conditional flag C 3 to the conditional flag C 2 , and moves the value of the conditional flag C 4 to the conditional flags C 3 and C 6 , (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

1 . A compiler apparatus that translates a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser unit operable to parse the source program;   an intermediate code conversion unit operable to convert the parsed source program into intermediate codes;   an optimization unit operable to optimize the intermediate codes; and   a code generation unit operable to convert the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   the optimization unit, when the intermediate codes include a loop, places an instruction in a prolog phase in the loop in a case where said loop is unrolled by means of software pipelining, the instruction being to be executed immediately before the loop.   
   
   
       2 . A compiler apparatus that translates a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser unit operable to parse the source program;   an intermediate code conversion unit operable to convert the parsed source program into intermediate codes;   an optimization unit operable to optimize the intermediate codes; and   a code generation unit operable to convert the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   the optimization unit, when the intermediate codes include a loop, places an instruction in an epilog phase in the loop in a case where said loop is unrolled by means of software pipelining, the instruction being to be executed immediately after the loop.   
   
   
       3 . A compiler apparatus that translates a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser unit operable to parse the source program;   an intermediate code conversion unit operable to convert the parsed source program into intermediate codes;   an optimization unit operable to optimize the intermediate codes; and   a code generation unit operable to convert the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   the optimization unit, when the intermediate codes include a conditional branch instruction, assigns the plurality of conditional execution flags so that a conditional execution flag used as a predicate for a conditional execution instruction in a case where a condition indicated by said conditional branch instruction is met, becomes different from a conditional execution flag used as a predicate for a conditional execution instruction in a case where said condition is not met.   
   
   
       4 . A compilation method for translating a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser step of parsing the source program;   an intermediate code conversion step of converting the parsed source program into intermediate codes;   an optimization step of optimizing the intermediate codes; and   a code generation step of converting the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   in the optimization step, when the intermediate codes include a loop, an instruction is placed in a prolog phase in the loop in a case where said loop is unrolled by means of software pipelining, the instruction being to be executed immediately before the loop.   
   
   
       5 . A compilation method for translating a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser step of parsing the source program;   an intermediate code conversion step of converting the parsed source program into intermediate codes;   an optimization step of optimizing the intermediate codes; and   a code generation step of converting the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   in the optimization step, when the intermediate codes include a loop, an instruction is placed in an epilog phase in the loop in a case where said loop is unrolled by means of software pipelining, the instruction being to be executed immediately after the loop.   
   
   
       6 . A compilation method for translating a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser step of parsing the source program;   an intermediate code conversion step of converting the parsed source program into intermediate codes;   an optimization step of optimizing the intermediate codes; and   a code generation step of converting the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   in the optimization step, when the intermediate codes include a conditional branch instruction, the plurality of conditional execution flags are assigned so that a conditional execution flag used as a predicate for a conditional execution instruction in a case where a condition indicated by said conditional branch instruction is met, becomes different from a conditional execution flag used as a predicate for a conditional execution instruction in a case where said condition is not met.   
   
   
       7 . A complier for translating a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser step of parsing the source program;   an intermediate code conversion step of converting the parsed source program into intermediate codes;   an optimization step of optimizing the intermediate codes; and   a code generation step of converting the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   in the optimization step, when the intermediate codes include a loop, an instruction is placed in a prolog phase in the loop in a case where said loop is unrolled by means of software pipelining, the instruction being to be executed immediately before the loop.   
   
   
       8 . A complier for translating a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser step of parsing the source program;   an intermediate code conversion step of converting the parsed source program into intermediate codes;   an optimization step of optimizing the intermediate codes; and   a code generation step of converting the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   in the optimization step, when the intermediate codes include a loop, an instruction is placed in an epilog phase in the loop in a case where said loop is unrolled by means of software pipelining, the instruction being to be executed immediately after the loop.   
   
   
       9 . A complier for translating a source program into a machine language program for a processor capable of executing instructions in parallel, comprising:
 a parser step of parsing the source program;   an intermediate code conversion step of converting the parsed source program into intermediate codes;   an optimization step of optimizing the intermediate codes; and   a code generation step of converting the optimized intermediate codes into machine language instructions,   wherein the processor stores a plurality of flags used as predicates for conditional execution instructions, and   in the optimization step, when the intermediate codes include a conditional branch instruction, the plurality of conditional execution flags are assigned so that a conditional execution flag used as a predicate for a conditional execution instruction in a case where a condition indicated by said conditional branch instruction is met, becomes different from a conditional execution flag used as a predicate for a conditional execution instruction in a case where said condition is not met.