Method for storing multiple levels of design data in a common database

Abstract

An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The common database includes entities, models, cells, pins, busses and nets. The data-flow graphs are stored as graphs, the nodes in a graph as cells, and the edges as busses. Physical design data is available by storing the cells in a model in a KD tree. This allows queries on cells in the netlist located in the layout within arbitrary areas.

1 . A method of storing data for use by an automated logic circuit design system comprising the steps of:
 providing a common database that allows for storage of data associated with automated circuit design;   performing at least one logical operation and at least one physical operation, with each operation accessing the common database and modifying the data therein, the at least one logical operation including at least one of logic synthesis and timing simulation operations and the at least one physical operation including at least one of physical placement and physical routing operations; and   wherein each of the logic synthesis, timing simulation, physical placement, and physical routing operations are performed and each operation accesses the common database and modifies the data stored therein.   
     
     
         2 . The method according to  claim 1  further including a step of making at least one area query. 
     
     
         3 . The method according to  claim 2  wherein the step of making at least one area query makes a plurality of area queries, with one of the plurality of area queries taking place after the logical operation and another one of the plurality of area queries taking place during the at least one physical operation. 
     
     
         4 . The method according to  claim 2 , wherein at least one of the area queries is made to verify a property of the circuit. 
     
     
         5 . The method according to  claim 4  wherein the property is a spacing between adjacent nets. 
     
     
         6 . The method according to  claim 5  wherein the spacing is used in order to simulate a timing of the circuit. 
     
     
         7 . The method according to  claim 4  wherein the property is adherence to design rules. 
     
     
         8 . The method according to  claim 7  wherein the design rule relates to spacing between diffusion regions in a substrate. 
     
     
         9 . The method according to  claim 7  wherein the design rule relates to pitch between metal lines. 
     
     
         10 . The method according to  claim 7  wherein the design rule relates to minimum widths of conductive regions. 
     
     
         11 . The method according to  claim 2  wherein the at least one area query is made when performing diagnostics. 
     
     
         12 . The method according to  claim 11  wherein the diagnostics include checking for electrical short circuiting. 
     
     
         13 . The method according to  claim 2  wherein the at least one area query is made to manipulate a portion of the circuit. 
     
     
         14 . The method according to  claim 13  wherein the manipulating of the portion of the circuit adds a buffer to the portion of the circuit to obtain proper timing for that portion of the circuit.