Process for forming differential spaces in electronics device integrated on a semiconductor substrate

Abstract

A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.

1 . A process, comprising:
 forming a first portion of an electronic device integrated on a semiconductor substrate, wherein forming the first portion includes forming first transistors each comprising a gate electrode projecting from the semiconductor substrate and respective source/drain regions;   forming a second portion of the electronic device by steps including forming second transistors each comprising a gate electrode projecting from the semiconductor substrate and respective source/drain regions;   forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the first and second portions;   forming a first mask covering the first portion;   removing first portions of the first conformal insulating layer not covered by the first mask;   removing the first mask;   forming a second conformal insulating layer of a second thickness on the first and second portions; and   forming first spacers of a first width on side walls of the gate electrodes of the first portion and second spacers of a second width on side walls of the gate electrodes of the second portion by removing the second portions of the first conformal insulating layer and portions of the second conformal insulating layer until the protective layer is exposed.   
   
   
       2 . The process of  claim 1  forming a further conformal insulating layer on the first and second portions before forming the first conformal insulating layer. 
   
   
       3 . The process of  claim 2 , wherein the further conformal insulating layer is of a thickness equal to about 15 nm. 
   
   
       4 . The process of  claim 2 , wherein the further conformal insulating layer is formed by an oxide layer. 
   
   
       5 . The process of  claim 1 , wherein the conformal insulating layers are formed by oxide layers and the protective layer is formed by a nitride layer. 
   
   
       6 . The process of  claim 1 , wherein the first thickness of the first conformal insulating layer is equal to about 60 nm, the second thickness of the second conformal insulating layer is equal to about 20 nm, and the protective layer is of a thickness equal to about 15 nm. 
   
   
       7 . The process of  claim 1 , wherein forming the first and second spacers includes anisotropically removing the second portions of the first conformal insulating layer and the portions of the second conformal insulating layer; and removing the first portions of the first conformal insulating layer includes isotropically removing the first portions of the first conformal insulating layer. 
   
   
       8 . The process of  claim 1 , wherein the second transistors are floating gate transistors which form non-volatile memory cells. 
   
   
       9 . A process, comprising:
 forming a first portion of an electronic device integrated on a semiconductor substrate, wherein forming the first portion includes forming first transistors each comprising a gate electrode projecting from the semiconductor substrate and respective source/drain regions;   forming a second portion of the electronic device by steps including forming second transistors each comprising a gate electrode projecting from the semiconductor substrate and respective source/drain regions;   forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the first and second portions;   forming first spacers on side walls of the gate electrodes by removing portions of the first conformal insulating layer until the protective layer is exposed to form;   forming a first mask covering the first portion;   removing the first spacers of the second portion while the first mask protects the first portion;   removing the first mask;   forming a second conformal insulating layer of a second thickness on the first and second portions; and   forming second spacers adjacent to the first spacers of the first portion and on the side walls of the gate electrodes of the second portion by removing portions of the second conformal insulating layer until the protective layer is exposed.   
   
   
       10 . The process of  claim 9 , further comprising forming a further conformal insulating layer on the first and second portions before forming the first conformal insulating layer. 
   
   
       11 . The process of  claim 10 , wherein the further conformal insulating layer is of a thickness equal to about 15 nm. 
   
   
       12 . The process of  claim 10 , wherein the further conformal insulating layer is formed by an oxide layer. 
   
   
       13 . The process of  claim 10 , wherein the first thickness of the first conformal insulating layer is equal to about 60 nm, the second thickness of the second conformal insulating layer is about 50 nm, the further conformal insulating layer is of a thickness equal to about 20 nm, and the protective layer is of a thickness equal to about 15 nm. 
   
   
       14 . The process of  claim 9 , wherein the conformal insulating layers are formed by oxide layers and the protective layer is formed by a nitride layer. 
   
   
       15 . The process of  claim 9 , wherein the second transistors are floating gate transistors which form a non-volatile memory cells. 
   
   
       16 . The process of  claim 9 , wherein the steps of removing the portions of the conformal insulating layers for forming the spacers are performed anisotropically, and the step of removing the spacers is performed isotropically. 
   
   
       17 . A process, comprising:
 forming a plurality of portions of an electronic device integrated on a semiconductor substrate wherein forming the plurality of portions includes forming respective transistors, each comprising a gate electrode projecting from the semiconductor substrate, and respective source/drain regions;   forming in cascade a protective layer and a first conformal insulating layer on the plurality of portions;   forming a first mask covering a first portion of the plurality;   removing portions of the first conformal insulating layer not covered by the first mask;   removing the first mask;   forming a second conformal insulating layer on the plurality of portions;   forming a second mask covering the first portion and a second portion of the plurality;   removing portions of the second conformal insulating layer not covered by the second mask;   removing the second mask;   forming a third conformal insulating layer on the plurality of portions; and   forming a plurality of spacers on respective side walls of the gate electrodes of the plurality of portions by removing the insulating layers until the protective layer is exposed.   
   
   
       18 . The process of  claim 17 , further comprising forming a further conformal insulating layer on the plurality of portions before forming the first conformal insulating layer. 
   
   
       19 . The process of  claim 18 , wherein the further conformal insulating layer is formed by an oxide layer. 
   
   
       20 . The process of  claim 17 , wherein the conformal insulating layers are formed by oxide layers and the protective layer is formed by a nitride layer. 
   
   
       21 . The process of  claim 17 , wherein removing the insulating layers until the protective layer is exposed is performed anisotropically, and the steps of removing portions of the conformal insulating layers not covered by the masks are performed isotropically. 
   
   
       22 . The process of  claim 17 , wherein the transistors of a third portion of the plurality are floating gate transistors forming non-volatile memory cells. 
   
   
       23 . A process, comprising:
 forming a plurality of portions of an electronic device integrated on a semiconductor substrate, wherein forming the plurality of portions includes forming respective transistors each comprising a gate electrode projecting from the semiconductor substrate and respective source/drain regions;   forming in cascade a protective layer and a first conformal insulating layer on the plurality of portions;   forming first spacers on side walls of the gate electrodes by removing the first conformal insulating layer until the protective layer is exposed;   forming a first mask covering a first portion of the plurality;   removing the spacers in second and third portions of the plurality while the first mask covers the first portion;   removing the first mask;   forming a second conformal insulating layer on the plurality of portions;   forming second spacers on the first spacers of the first portion and on the side walls of the gate electrodes of the second and third portions by removing the second conformal insulating layer until the protective layer is exposed;   forming a second mask covering the first and second portions   removing the second spacers from the third portion while the second mask covers the first and second portions;   removing the second mask;   forming a third conformal insulating layer on the plurality of portions; and   forming third spacers adjacent to the second spacers in the first and second portions and on the side walls of the gate electrodes of the third portion by removing the third conformal insulating layer until the protective layer is exposed.   
   
   
       24 . The process of  claim 23 , further comprising forming a further conformal insulating layer on the first, second, and third portions before forming the first conformal insulating layer. 
   
   
       25 . The process of  claim 24 , wherein the further conformal insulating layer is formed by an oxide layer. 
   
   
       26 . The process of  claim 23 , wherein the conformal insulating layers are formed by oxide layers and the protective layer is formed by a nitride layer. 
   
   
       27 . The process according to  claim 23 , wherein the transistors of the third portion are floating gate transistors which form non-volatile memory cells. 
   
   
       28 . The process according to  claim 23 , wherein the steps of removing the conformal insulating layers for forming the spacers are performing anisotropically, and the steps of removing the spacers are performed isotropically.