US2008203572A1PendingUtilityA1
Semiconductor device and method of fabricating the same
Est. expiryFeb 27, 2024(expired)· nominal 20-yr term from priority
H10P 14/46H10W 20/425H10W 20/057H10W 20/47H10W 20/037H10W 20/056
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Claims
Abstract
The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer 108 , and interconnects 160 filled in grooves formed in the insulating interlayer, comprising a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140 , which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.
Claims
exact text as granted — not AI-modified1 . A method of fabricating a semiconductor device having an interconnect composed of a copper layer mainly composed of copper, on a semiconductor substrate, the method comprising the steps of:
forming an insulating interlayer on said semiconductor substrate, said insulating interlayer having a low-dielectric-constant layer with a dielectric constant smaller than that of silicon oxide and, on said low-dielectric-constant layer, an insulating layer having a mechanical strength larger than that of said low-dielectric-constant layer; forming a groove in said insulating interlayer through said insulating layer and said low-dielectric-constant layer; filling said groove with said copper layer; removing a top portion of said copper layer to a predetermined depth; and depositing a metal layer having a heat expansion coefficient smaller than that of said copper layer, on said copper layer in said groove, to thereby form said interconnect, said metal layer being thicker than said insulating layer.
2 . The method of claim 1 , wherein said metal layer and said insulating layer each have a top surface at a same level in the device.
3 . The method of claim 1 , wherein said metal layer has a top surface that extends above a top surface of said insulating layer.
4 . The method of claim 3 , further comprising the step of forming a barrier layer inside said groove between said copper layer and said insulating interlayer, said barrier layer not extending above the top surface of said insulating interlayer.
5 . A semiconductor device comprising:
an insulating interlayer having a top surface; and an interconnect filled in a groove that extends through the top surface of said insulating interlayer, said interconnect comprising a copper layer mainly composed of copper and having a thickness smaller than the depth of said groove, and a metal layer having a heat expansion coefficient smaller than that of said copper layer, formed on said copper layer, said metal layer having a top surface that extends above the top surface of said insulating interlayer.
6 . The semiconductor device of claim 5 , further comprising a barrier layer inside said groove between said copper layer and said insulating interlayer, said barrier layer not extending above the top surface of said insulating interlayer.Join the waitlist — get patent alerts
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