Semiconductor device and manufacturing method thereof

Abstract

In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

1 . A semiconductor device which has a capacitive element comprising:
 a first metallic interconnect layer where a plurality of first metallic interconnects are formed;   a second interconnect layer where a plurality of second metallic interconnects and a lower electrode of said capacitive element including a film made of the same material as said second metallic interconnect are formed;   a capacitive dielectric film of said capacitive element formed over said lower electrode; and   an upper electrode of said capacitive element formed over said capacitive dielectric film,   wherein said first metallic interconnect, said second metallic interconnect, and said lower electrode have a metallic film and an upper barrier film formed over said metallic film, respectively,   wherein the film thickness of each said upper barrier film of said second metallic interconnect and said lower electrode is thicker than the film thickness of said upper barrier film of said first metallic interconnect.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein
 each said metallic film of said first metallic interconnect, said second metallic interconnect, and said lower electrode is a film which includes aluminum as a main component.   
   
   
       3 . The semiconductor device according to  claim 2 , wherein
 each said upper barrier film of said first metallic interconnect, said second metallic interconnect, and said lower electrode is a stacked film where a titanium film and a titanium nitride film are deposited, in order, from the bottom.   
   
   
       4 . The semiconductor device according to  claim 3 , wherein
 the film thickness of said upper barrier film of said second metallic interconnect and said lower electrode is 110 nm or more.   
   
   
       5 . The semiconductor device according to  claim 4 , wherein
 the film thickness of said upper barrier film of said second metallic interconnect and said lower electrode is 160 nm or more.   
   
   
       6 . A semiconductor device comprising a capacitive element,
 wherein said capacitive element has a lower electrode, a capacitive dielectric film formed over said lower electrode, and an upper electrode formed over said capacitive dielectric film,   wherein said lower electrode has a metallic film and an upper barrier film formed over said metallic film, and   wherein the film thickness of said upper barrier film is 110 nm or more.   
   
   
       7 . The semiconductor device according to  claim 6 , wherein
 said metallic film is a film including aluminum as a main component.   
   
   
       8 . The semiconductor device according to  claim 7 , wherein
 said upper barrier film is a stacked film where a titanium film and a titanium nitride film are deposited, in order, from the bottom.   
   
   
       9 . The semiconductor device according to  claim 6 , wherein
 the film thickness of said upper barrier film is 160 nm or more.   
   
   
       10 . A semiconductor device according to  claim 9 , wherein
 said metallic film is a film including aluminum as a main component.   
   
   
       11 . The semiconductor device according to  claim 10 , wherein
 said upper barrier film is a stacked film where a titanium film and a titanium nitride film are deposited, in order, from the bottom.   
   
   
       12 . A manufacturing method of a semiconductor device which has a capacitive element comprising the steps of:
 forming a first metallic film over a first interpoly dielectric film;   forming a first upper barrier film over said first metallic film;   forming a plurality of first metallic interconnects and a lower electrode of said capacitive element by processing a stacked film of said first metallic film and said first upper barrier film;   forming a second interpoly dielectric film which covers said plurality of first metallic interconnects and said lower electrode;   partially removing said second interpoly dielectric film and exposing a part of the upper face of said first upper barrier film of said lower electrode;   forming a capacitive dielectric film of said capacitive element over exposed said first barrier film of said lower electrode;   forming a second metallic film over said second interpoly dielectric film and said capacitive dielectric film;   forming a second upper barrier film over said second metallic film; and   forming a plurality of second metallic interconnects and an upper electrode of said capacitive element by processing a stacked film of said second metallic film and said second upper barrier film,   wherein the film thickness of said first barrier film is made thicker than the film thickness of said second upper barrier film.   
   
   
       13 . The semiconductor device according to  claim 12 , wherein
 said first metallic film and said second metallic film are formed of films including aluminum as a main component.   
   
   
       14 . The semiconductor device according to  claim 13 , wherein
 said first upper barrier film and said second upper barrier film are formed of a stacked film where a titanium film and a titanium nitride film are deposited, in order, from the bottom.   
   
   
       15 . The semiconductor device according to  claim 14 , wherein
 said first upper barrier film is formed to be a film thickness of 110 nm or more.   
   
   
       16 . The semiconductor device according to  claim 15 , wherein
 said first upper barrier film is formed to be a film thickness of 160 nm or more.