Field effect transistor arrangement and method of producing a field effect transistor arrangement

Abstract

A field effect transistor arrangement and a fabrication method thereof. The field effect transistor arrangement includes: a substrate having a first crystal surface orientation; a first layer formed above at least a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation; a second layer formed above at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation; a first buried oxide layer formed between the first layer and the substrate; a second buried oxide layer formed between the second layer and the substrate; a first field effect transistor formed in or on the first layer, the first field effect transistor having a first conductivity type; and a second field effect transistor formed in or on the second layer, the second field effect transistor having a second conductivity type different from the first conductivity type.

1 . A field effect transistor arrangement, comprising:
 a substrate having a first crystal surface orientation;   a first layer formed above at least a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation;   a second layer formed above at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation;   a first buried oxide layer formed between the first layer and the substrate;   a second buried oxide layer formed between the second layer and the substrate;   a first field effect transistor formed in or on the first layer, the first field effect transistor having a first conductivity type; and   a second field effect transistor formed in or on the second layer, the second field effect transistor having a second conductivity type different from the first conductivity type.   
   
   
       2 . The field effect transistor arrangement as claimed in  claim 1 , wherein at least one of the substrate, the first layer and the second layer comprises silicon material. 
   
   
       3 . The field effect transistor arrangement as claimed in  claim 2 , wherein the substrate is a silicon handle wafer. 
   
   
       4 . The field effect transistor arrangement as claimed in  claim 1 , wherein the first crystal surface orientation is a (110) crystal surface orientation and wherein the second crystal surface orientation is a (100) crystal surface orientation. 
   
   
       5 . The field effect transistor arrangement as claimed in  claim 4 , wherein the first field effect transistor is an NMOS field effect transistor, and wherein the second field effect transistor is a PMOS field effect transistor. 
   
   
       6 . The field effect transistor arrangement as claimed in  claim 1 , wherein the second buried oxide layer is formed by forming micro-cavities in the second layer and oxidizing the micro-cavities. 
   
   
       7 . A method of producing a field effect transistor arrangement, comprising:
 providing a substrate having a first crystal surface orientation;   forming a first layer above at least a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation;   forming a second layer on at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation;   forming a first buried oxide layer between the substrate and the first layer;   forming micro-cavities in the second layer and oxidizing the micro-cavities, thereby forming a second buried oxide layer between the substrate and the second layer;   forming a first field effect transistor in or on the first layer, the first field effect transistor having a first conductivity type; and   forming a second field effect transistor in or on the second layer, the second field effect transistor having a second conductivity type.   
   
   
       8 . The method as claimed in  claim 7 , wherein the second layer is formed by an epitaxial growth process. 
   
   
       9 . The method as claimed in  claim 7 , wherein the micro-cavities are formed in the second layer by implanting light ions into the second layer. 
   
   
       10 . The method as claimed in  claim 9 , wherein the light ions are selected from a group of ions consisting of:
 H 2   +  ions;   He +  ions;   F +  ions;   Ne +  ions;   Cl +  ions; and   Ar +  ions.   
   
   
       11 . The method as claimed in  claim 9 , wherein the light ions are implanted with an implantation dose of approximately between 10 15  cm −2  and 10 18  cm −2 . 
   
   
       12 . The method as claimed in  claim 9 , wherein the light ions have an implantation energy of approximately between 10 keV and 150 keV. 
   
   
       13 . The method as claimed in  claim 7 , wherein after formation of the micro-cavities and before oxidation of the micro-cavities, oxygen ions are implanted into the second layer, thereby forming oxygen rich precipitates in the second layer. 
   
   
       14 . The method as claimed in  claim 13 , wherein the oxygen ions are implanted with an implantation dose of approximately between 10 15  cm −2  and 10 18  cm −2 . 
   
   
       15 . The method as claimed in  claim 13 , wherein the oxygen ions have an implantation energy of approximately between 10 keV and 400 keV. 
   
   
       16 . The method as claimed in  claim 7 , wherein the micro-cavities are oxidized by a high-temperature treatment and introducing oxygen into the micro-cavities. 
   
   
       17 . The method as claimed in  claim 16 , wherein the substrate is heated to a temperature of approximately between 1000° C. and 1350° C. in the context of the high-temperature treatment. 
   
   
       18 . The method as claimed in  claim 16 , wherein the substrate is heated for a duration of approximately between 30 min and 2 h in the context of the high-temperature treatment. 
   
   
       19 . The method as claimed in  claim 16 , wherein the oxygen is introduced into the micro-cavities by thermal indiffusion or implantation. 
   
   
       20 . The method as claimed in  claim 7 , wherein at least one of the substrate, the first layer and the second layer comprises silicon. 
   
   
       21 . The method as claimed in  claim 20 , wherein a silicon handle wafer is used as the substrate. 
   
   
       22 . The method as claimed in  claim 7 , wherein the first crystal surface orientation is a (110) crystal surface orientation and wherein the second crystal surface orientation is a (100) crystal surface orientation. 
   
   
       23 . A method of producing a semiconductor element, comprising:
 forming micro-cavities in a substrate;   oxidizing the micro-cavities, thereby forming a buried oxide layer in the substrate;   forming the semiconductor element in or on a portion of the substrate above the buried oxide layer.   
   
   
       24 . The method as claimed in  claim 23 , wherein light ions are implanted into the substrate, thereby forming the micro-cavities in the substrate. 
   
   
       25 . The method as claimed in  claim 23 , wherein after formation of the micro-cavities and before oxidation of the micro-cavities, oxygen ions are implanted into the substrate, thereby formimg oxygen rich precipitates in the substrate. 
   
   
       26 . The method as claimed in  claim 23 , wherein the micro-cavities are oxidized by a high-temperature treatment and introducing oxygen into the micro-cavities. 
   
   
       27 . A semiconductor element, comprising:
 a substrate; and   a buried oxide layer formed in the substrate, wherein the buried oxide layer is formed by forming micro-cavities in the substrate and oxidizing the micro-cavities.