Clock buffer circuit of semiconductor device

Abstract

A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.

1 . A clock buffer circuit of a semiconductor device comprising:
 a first clock buffer configured to receive and buffer a normal-phase clock signal;   a second clock buffer configured to receive and buffer a reverse-phase clock signal; and   an internal clock generator configured to generate an internal clock signal in response to output signals from the first and second clock buffers.   
   
   
       2 . The clock buffer circuit according to  claim 1 , wherein the internal clock generator generates a rising edge of the internal clock signal at a rising edge of the buffered signal from the first clock buffer, and a falling edge of the internal clock signal at a rising edge of the buffered signal from the second clock buffer. 
   
   
       3 . The clock buffer circuit according to  claim 2 , wherein the internal clock generator comprises an edge trigger circuit. 
   
   
       4 . The clock buffer circuit according to  claim 3 , wherein the edge trigger circuit comprises:
 a first inverter for buffering the output signal from the first clock buffer;   a first delay for delaying an output signal from the first inverter;   a second delay for delaying the output signal from the second clock buffer;   a driver for performing a pull-up driving operation in response to the output signal from the first inverter and an output signal from the first delay or a pull-down driving operation in response to the output signal from the second clock buffer and an output signal from the second delay;   a latch for latching an output signal from the driver; and   a second inverter for buffering an output signal from the latch.   
   
   
       5 . The clock buffer circuit according to  claim 4 , wherein the driver comprises:
 a first pull-up device for performing the pull-up driving operation in response to the output signal from the first delay;   a second pull-up device connected in parallel to the first pull-up device, the second pull-up device performing the pull-up driving operation in response to the output signal from the first inverter;   a first pull-down device for performing the pull-down driving operation in response to the output signal from the second clock buffer; and   a second pull-down device connected in parallel to the first pull-down device, the second pull-down device performing the pull-down driving operation in response to the output signal from the second delay.   
   
   
       6 . The clock buffer circuit according to  claim 4 , wherein each of the first delay and second delay comprises an odd number of inverters. 
   
   
       7 . The clock buffer circuit according to  claim 3 , wherein the edge trigger circuit comprises:
 a first logic circuit for performing a logic operation with respect to the output signal from the first clock buffer;   a second logic circuit for performing a logic operation with respect to the output signal from the second clock buffer;   a first driver for performing a pull-up or pull-down driving operation in response to an output signal from the first logic circuit and an inverted version of an output signal from the second logic circuit;   a second driver for performing the pull-up or pull-down driving operation in response to an inverted version of the output signal from the first logic circuit and the output signal from the second logic circuit;   a first output unit for outputting an output signal from the first driver; and   a second output unit for outputting an output signal from the second driver.   
   
   
       8 . The clock buffer circuit according to  claim 7 , wherein the first logic circuit comprises:
 a first delay for delaying the output signal from the first clock buffer; and   a first logic device for performing a NAND operation with respect to the output signal from the first clock buffer and an output signal from the first delay.   
   
   
       9 . The clock buffer circuit according to  claim 8 , wherein the second logic circuit comprises:
 a second delay for delaying the output signal from the second clock buffer; and   a second logic device for performing the NAND operation with respect to the output signal from the second clock buffer and an output signal from the second delay.   
   
   
       10 . The clock buffer circuit according to  claim 7 , wherein the first driver comprises:
 a first pull-up device for performing the pull-up driving operation in response to the output signal from the first logic circuit;   a first pull-down device for performing the pull-down driving operation in response to the output signal from the first logic circuit; and   a second pull-down device connected in parallel to the first pull-down device, the second pull-down device performing the pull-down driving operation in response to the inverted version of the output signal from the second logic circuit.   
   
   
       11 . The clock buffer circuit according to  claim 10 , wherein the second driver comprises:
 a second pull-up device for performing the pull-up driving operation in response to the output signal from the second logic circuit;   a third pull-down device for performing the pull-down driving operation in response to the output signal from the second logic circuit; and   a fourth pull-down device connected in parallel to the third pull-down device, the fourth pull-down device performing the pull-down driving operation in response to the inverted version of the output signal from the first logic circuit.   
   
   
       12 . The clock buffer circuit according to  claim 7 , wherein the first output unit comprises:
 a first latch for latching the output signal from the first driver; and   a first inverter for buffering an output signal from the first latch.   
   
   
       13 . The clock buffer circuit according to  claim 12 , wherein the second output unit comprises:
 a second latch for latching the output signal from the second driver; and   a second inverter for buffering an output signal from the second latch.   
   
   
       14 . The clock buffer circuit according to  claim 1 , wherein the first clock buffer comprises a differential amplifier for receiving the normal-phase clock signal as an input signal and the reverse-phase clock signal as a reference signal and amplifying and buffering a difference between the received signals. 
   
   
       15 . The clock buffer circuit according to  claim 1 , wherein the second clock buffer comprises a differential amplifier for receiving the reverse-phase clock signal as an input signal and the normal-phase clock signal as a reference signal and amplifying and buffering a difference between the received signals. 
   
   
       16 . A clock buffer circuit of a semiconductor device comprising an internal clock generator for generating a rising edge of an internal clock signal using a first clock signal which is a buffered version of a normal-phase clock signal, and a falling edge of the internal clock signal using a second clock signal which is a buffered version of a reverse-phase clock signal. 
   
   
       17 . The clock buffer circuit according to  claim 16 , wherein the internal clock generator generates the rising edge of the internal clock signal at a rising edge of the first clock signal, and the falling edge of the internal clock signal at a rising edge of the second clock signal. 
   
   
       18 . The clock buffer circuit according to  claim 16 , wherein the internal clock generator comprises an edge trigger circuit.