Data processor

Abstract

An object of the present invention is to achieve fast data processing. A unit (FF) is included for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length). Depending on whether instruction reading is performed in units of 16 bits or 32 bits, increment values (+2 and +4) by which a program counter (PC) is incremented are switched. Data reading or writing is performed in units of a given data length irrespective of the selecting unit. When the CPU issues a request for instruction reading in units of 16 bits or 32 bits or for data reading or writing, a bus control unit performs reading or writing a predetermined number of times according to a bus width designated for a resource located at an address specified in the request. The bus control unit causes the CPU to wait until an instruction of 16 or 32 bits long (read data) requested by the CPU gets ready.

1 - 11 . (canceled) 
     
     
         12 . A data processor comprising:
 an instruction executing unit which reads and decodes an instruction, and executes the instruction according to the result of the decoding,   wherein said instruction executing unit includes a first storing unit and a second storing unit that store an instruction code,   wherein said second storing unit stores a branch target instruction read in response to a delay branch instruction, and   wherein said first storing unit stores a previous branch target instruction, and when a delay slot instruction is terminated, said first storing unit is cleared.   
     
     
         13 . A data processor according to  claim 12 ,
 said instruction executing unit further comprising:   a prefetch counter; and   a temporary register unit used to temporarily store information,   wherein the temporary register unit stores a branch target address or a value produced by incrementing the branch target address in response to a delay branch instruction,   wherein said prefetch counter stores a previous branch target address, and   wherein said prefetch counter is usable during execution of a delay slot instruction, and when the delay slot instruction is terminated, the contents of said temporary register unit or the value produced by incrementing the branch target address is pre-set in said prefetch counter.   
     
     
         14 . A data processor according to  claim 12 , wherein when said instruction executing unit controls execution of a delay slot instruction, said instruction executing unit disables instruction reading in an execution state of the delay slot instruction in which an instruction code thereof is read and an execution state thereof in which an effective address thereof is calculated. 
     
     
         15 . A data processor according to  claim 12 , wherein said instruction executing unit is able to execute a branch instruction which is the same addressing mode as the delay branch instruction and which does not cause a delay branch. 
     
     
         16 - 21 . (canceled)