Duty cycle measurment circuit for measuring and maintaining balanced clock duty cycle

Abstract

A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

1 . A circuit for measuring timing uncertainties in a clock signal, said circuit comprising:
 a local clock buffer receiving a global clock and providing a local clock;   a delay line receiving said local clock, said local clock traversing said delay line and being provided as an output at output taps along said traversed delay line; and   a register clocked by said local clock and capturing the state of said output taps, progression of said local clock through said delay line being captured in said register.   
   
   
       2 . A circuit as in  claim 1  wherein said delay line is at least 3 global clock cycles long. 
   
   
       3 . A circuit as in  claim 2  wherein said delay line taps are evenly spaced along said delay line and a clock edge in said delay line is identified by a matched state at a pair of adjacent said delay line taps. 
   
   
       4 . (canceled) 
   
   
       5 . A circuit as in  claim 3  wherein said local clock is a complementary pair of local clocks, said delay line receiving a first local clock of said complementary pair of local clocks. 
   
   
       6 . A circuit as in  claim 3  wherein said delay line is a number (N) of series connected inverters, said local clock being an input to said series connected inverters. 
   
   
       7 . A circuit as in  claim 6  wherein said register is an N bit register, each bit connected to one of said delay line taps and receiving an output of one of said series connected inverters. 
   
   
       8 . A circuit as in  claim 6  wherein one of said series connected inverters is an adjustable delay inverter selectably varying delay in said delay line. 
   
   
       9 . A circuit as in  claim 6  wherein said register is an N bit register, said circuit further comprising:
 a second register, said second register being an N−1 bit register selectively receiving the contents of said N bit register.   
   
   
       10 . A circuit as in  claim 9 , said circuit further comprising:
 a compare receiving the contents of said second register and detecting clock edges falling outside of an acceptable range.   
   
   
       11 . A circuit as in  claim 10  wherein said compare
 compares second register bit patterns against a selectable signature bit pattern indicating expected edge locations, and   generates an interrupt signal for a service processor if a clock edge is determined to occur other than in an expected edge location.   
   
   
       12 . A circuit as in  claim 9  further comprising:
 an adjustable delay receiving an output from said multiplexor and selectably delaying said output.   
   
   
       13 . A circuit as in  claim 9  wherein contents of said second register may be held over a selected number of clock cycles. 
   
   
       14 . A circuit as in  claim 9  wherein contents of said second register may be shifted out in a functional shift without stopping the clocks or using a scan path. 
   
   
       15 . A circuit as in  claim 9  wherein clock edges may be accumulated over a selected number of clock cycles. 
   
   
       16 . A circuit as in  claim 15  wherein accumulated said clock edges indicate a clock jitter range. 
   
   
       17 . A circuit as in  claim 16  wherein accumulated said clock edges indicate clock skew and power supply noise related timing uncertainty in each cycle. 
   
   
       18 . A circuit as in  claim 3  measuring jitter, skew and power supply noise related timing uncertainty in each cycle. 
   
   
       19 . A circuit as in  claim 3  further comprising a start counter delaying data logging until after a selected number of clock cycles. 
   
   
       20 - 35 . (canceled)