Method for built in self test for measuring total timing uncertainty in a digital data path

Abstract

A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

1 - 30 . (canceled) 
   
   
       31 . A method of characterizing circuit sensitivity to supply noise, said method comprising the steps of:
 a) determining a baseline circuit delay;   b) reducing circuit supply voltage by a selected voltage step;   c) determining a circuit delay at the reduced said supply voltage;   d) determining whether said reduced supply voltage is at a lower limit; and,   e) returning to reducing step (b) until said lower limit is found in determining step (e).   
   
   
       32 . A method of characterizing circuit sensitivity to supply noise as in  claim 31 , said method further comprising the steps of:
 f) increasing circuit supply voltage by a selected voltage step;   g) determining a circuit delay at the increased said supply voltage;   h) determining whether said increased supply voltage is at an upper limit; and,   j) returning to increasing step (f) until said upper limit is found in determining step (h).   
   
   
       33 . A method of characterizing circuit sensitivity to supply noise as in  claim 32 , wherein said circuit delay determined in steps (c) and (g) is an inverter count indicating a number of inverters traversed by a signal propagating through a series of inverters and said method further comprising the step of:
 k) determining an inverter to supply voltage change relationship.   
   
   
       34 . A method of characterizing supply noise comprising characterizing circuit sensitivity to supply noise as in  claim 33 , said method further comprising the steps of:
 l) locating a supply noise event; and   m) scanning through said supply noise event and logging said inverter count at each cycle during said supply noise event.   
   
   
       35 . A method of characterizing supply noise comprising characterizing circuit sensitivity to supply noise as in  claim 34 , wherein the scanning step (m) comprises the step of:
 i) determining said inverter count after a first number (N) of cycles;   ii) incrementing said number and determining said inverter count after the incremented said number;   iii) checking whether said incremented number indicates that said supply noise event has passed; and,   iv) returning to incrementing step (ii) until in step (iii) said supply noise event is determined to have passed.   
   
   
       36 . A method of measuring circuit timing uncertainties in a clock signal, said method comprising the steps of:
 receiving a global clock at a local clock buffer;   providing an output clock from said local clock buffer and a remote clock to a multiplexor;   selecting either of said output clock and said remote clock as a local clock from said multiplexor, said local clock being an input to a delay line, said local clock traversing said delay line and being provided as an output at output taps along said traversed delay line; and   clocking a register with said output clock, said register capturing progression of said local clock through said delay line in said register as the state of said output taps.   
   
   
       37 . A method as in  claim 36  wherein said delay line is at least 3 global clock cycles long. 
   
   
       38 . A method as in  claim 37  wherein said delay line taps are evenly spaced along said delay line, said method further comprising the steps of:
 comparing states at pairs of adjacent said delay line taps; and   identifying matched said pairs, each matched pair identifying a clock edge in said delay line.   
   
   
       39 . A method as in  claim 36  wherein said output clock is a complementary pair of local clocks, said delay line receiving a first local clock of said complementary pair of local clocks and said remote clock is a remote said first local clock from a second said local clock buffer. 
   
   
       40 . A method as in  claim 36  wherein said delay line is a number (N) of series connected inverters, and said local clock is provided as an input to said series connected inverters. 
   
   
       41 . A method as in  claim 40  wherein said register is an N bit register, and an output of each of said series connected inverters is provided as an input to a corresponding register bit. 
   
   
       42 . A method as in  claim 40  wherein one of said series connected inverters is an adjustable delay inverter, and said method further comprises the step of selectably varying delay in said delay line. 
   
   
       43 . A method as in  claim 36  wherein said register is an N bit register, said method further comprising the step of:
 selectively providing the contents of said N bit register to a second register, said second register being an N−1 bit register.   
   
   
       44 . A method as in  claim 43 , said method further comprising the steps of:
 comparing the contents of said second register; and   identifying clock edges falling outside of an acceptable range.   
   
   
       45 . A method as in  claim 44  wherein said comparing step comprises the steps of:
 comparing second register bit patterns against a selectable signature bit pattern indicating expected edge locations, and if a clock edge is determined to occur other than in an expected edge location   generating an interrupt signal for a service processor.   
   
   
       46 . A method as in  claim 43  further comprising the step of:
 providing said local clock to an adjustable delay and selectably delaying said output, said selectably delayed output being a time shifted local clock.   
   
   
       47 . A method as in  claim 43  further comprising the step of holding contents of said second register over a selected number of clock cycles. 
   
   
       48 . A method as in  claim 43  further comprising the step of shifting out the contents of said second register in a functional shift without stopping the clocks or using a scan path. 
   
   
       49 . A method as in  claim 43  further comprising the step of accumulating clock edges over a selected number of clock cycles. 
   
   
       50 . A method as in  claim 49  further comprising the step of determining a clock jitter range from accumulated said clock edges. 
   
   
       51 . A method as in  claim 49  further comprising the step of determining clock skew and power supply noise related timing uncertainty in each cycle from accumulated said clock edges. 
   
   
       52 . A method as in  claim 36  further comprising the step of measuring jitter, skew and power supply noise related timing uncertainty in each cycle. 
   
   
       53 . A method as in  claim 36  further comprising the step of delaying data logging until after a selected number of clock cycles responsive to a start counter.