Dynamic leakage control using selective back-biasing

Abstract

Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first power rail is coupled to an existing power supply and the second power rail is coupled to a separate adjustable voltage regulator. A separate voltage regulator may also be provided for the first power rail. A hardware-based state machine or software process is programmed to detect the occurrence of one or more modes of operation and adjust the voltage regulators for the first and second power rails to either enable or disable the back biasing state of the circuit, or alter the threshold voltage of the circuit within a specified voltage range.

1 . A method of controlling leakage current in a circuit, comprising:
 responsive to a change in a device from a first state to a second state, reducing an operating frequency provided by a system clock to the circuit from a first frequency to a second frequency; and   providing a back bias voltage to the circuit to effectively reduce a threshold voltage of the circuit along a voltage range between a first threshold voltage value to a second voltage value in response to the change in the device.   
   
   
       2 . The method of  claim 1 , wherein the first state comprises an active state of the circuit and the second state comprises a standby state of the circuit. 
   
   
       3 . The method of  claim 2 , wherein the standby state is detected by the presence of one or more indicators. 
   
   
       4 . The method of  claim 3 , wherein one of the one or more indicators comprises detecting a static screen display. 
   
   
       5 . The method of  claim 4 , further comprising detecting the persistence of an image displayed on a display device coupled to the circuit for a specified number of clock cycles of the system clock. 
   
   
       6 . The method of  claim 4  wherein the one or more indicators are selected from the group consisting essentially of: one or more returned busy signals, sleep mode flag activation, reduction in power draw, and reduced buffer activity. 
   
   
       7 . The method of  claim 2 , wherein the back bias voltage comprises a negative voltage applied to a body terminal of at least one transistor of the circuit. 
   
   
       8 . The method of  claim 7 , wherein the back bias voltage is provided to the at least one transistor through a first voltage regulator circuit coupled to a negative back bias voltage supply rail, the first voltage regulator controlled by a bias generator circuit in response to the detected change of state. 
   
   
       9 . The method of  claim 7 , wherein the back bias voltage further comprises a positive voltage applied to the body terminal of the at least one transistor of the circuit. 
   
   
       10 . The method of  claim 9 , wherein the back bias voltage is provided to the at least one transistor through a second voltage regulator circuit coupled to a positive back bias voltage supply rail, the second voltage regulator controlled by the bias generator circuit in response to the detected change of state. 
   
   
       11 . The method of  claim 10 , wherein the second voltage regulator circuit is configured to switch the back bias voltage along a voltage range from a third value to a fourth value. 
   
   
       12 . A circuit comprising:
 a condition detector, detecting a change of state of the circuit from a first state to a second state;   a state machine coupled to the condition generator, generating a control signal in response to the change of state;   a voltage regulator coupled to the state machine, reducing an operating frequency from a first frequency to a second frequency; and   a bias generator coupled to the voltage regulator, providing a back bias voltage to the circuit to effectively reduce a threshold voltage of the circuit along a voltage range between a first threshold voltage value to a second voltage value in response to the control signal.   
   
   
       13 . The circuit of  claim 12  wherein the first state comprises an active state of the circuit and the second state comprises a standby state of the circuit, and the standby state is detected by the presence of one or more indicators. 
   
   
       14 . The circuit of  claim 11 , wherein the circuit comprises at least one transistor, and further wherein the back bias voltage is selected from the group consisting of: a negative voltage applied to a body terminal of the at least one transistor of the circuit, and a positive voltage applied to the body terminal of the at least one transistor of the circuit. 
   
   
       15 . The circuit of  claim 14 , wherein the circuit comprises a circuit within an application specific integrated circuit device mounted on a printed-circuit board. 
   
   
       16 . The circuit of  claim 15 , wherein the circuit comprises at least a portion of a graphics processing unit. 
   
   
       17 . A method of controlling leakage current in a circuit, comprising:
 responsive to a change in the circuit from a first state to a second state, reducing an operating frequency provided by a system clock to the circuit from a first frequency to a second frequency; and   reducing a supply voltage to the circuit to effectively reduce a leakage current flowing through the circuit, along a range from a first supply voltage value to a second supply voltage value in response to the change in the circuit.   
   
   
       18 . The method of  claim 17 , wherein the first state comprises an active state of the circuit and the second state comprises a standby state of the circuit. 
   
   
       19 . The method of  claim 18 , wherein the standby state is detected by the presence of one or more indicators. 
   
   
       20 . The method of  claim 19 , wherein one of the one or more indicators comprises detecting a static screen display. 
   
   
       21 . The method of  claim 20 , further comprising detecting the persistence of an image displayed on a display device coupled to the circuit for a specified number of clock cycles of the system clock. 
   
   
       22 . The method of  claim 20  wherein the one or more indicators are selected from the group consisting essentially of one or more returned busy signals, sleep mode flag activation, reduction in power draw, and reduced buffer activity. 
   
   
       23 . The method of  claim 2 , wherein the first supply voltage value comprises a maximum supply voltage provided to a drain terminal of at least one transistor of the circuit. 
   
   
       24 . The method of  claim 23 , wherein the first supply voltage value is provided to the at least one transistor through a voltage regulator circuit controlled by a condition detection circuit in response to the detected change of state. 
   
   
       25 . The method of  claim 17 , wherein the circuit comprises a circuit within an application specific integrated circuit device mounted on a printed-circuit board. 
   
   
       26 . The method of  claim 25 , wherein the circuit comprises at least a portion of a graphics processing unit.