Phase alignment mechanism for minimizing the impact of integer-channel interference in a phase locked loop

Abstract

A novel and useful apparatus for and method of minimizing the impact of interference on the phase error performance in a phase locked loop (PLL) at integer channels by adjustment of the phase of the interfering signal such that its impact on the reference signal is minimized. Phase control is achieved by use of the digital architecture of the ADPLL and its insensitivity to an arbitrary phase bias introduced between its digitally represented output and reference phase signals. The optimal phase relationship for each integer channel is determined through a calibration procedure in which the phase is swept and the optimal phase is recorded. Before the transmission of a payload on an integer channel, the phase relationship between the output RF signal and the input reference signal is adjusted to the value found to be optimal for that frequency, based on the values previously recorded during the calibration procedure.

1 . A method of minimizing the impact of interference to a frequency reference from a radio frequency (RF) signal, said method comprising steps of:
 determining a desired phase relationship between said frequency reference input and said RF signal; and   adjusting the phase of said RF signal in accordance with said desired phase relationship.   
   
   
       2 . The method according to  claim 1 , wherein said step of adjusting substantially satisfies said desired phase relationship. 
   
   
       3 . The method according to  claim 1 , wherein said interference impact comprises excessive jitter induced onto said input reference signal resulting in corresponding distortion suffered at the output of the frequency synthesizer. 
   
   
       4 . The method according to  claim 1 , wherein said RF signal comprises a carrier signal of a wireless transmitter employing digital modulation. 
   
   
       5 . The method according to  claim 4 , wherein said RF signal comprises a harmonic of said carrier signal. 
   
   
       6 . The method according to  claim 1 , wherein said step of determining comprises:
 sweeping the phase relationship between said RF and frequency reference clock signals with a phase step;   assessing PLL performance by evaluation of said phase error samples; and   determining an optimum phase relationship and storing its location in a calibration table as a desired phase.   
   
   
       7 . The method according to  claim 1 , further comprising the step of measuring the phase relationship between said frequency reference input and said RF signal, wherein said phase is adjusted in accordance with said phase relationship measurements and said predetermined desired phase relationship. 
   
   
       8 . The method according to  claim 1 , wherein said step of adjusting comprises the step of temporarily changing the frequency of said RF signal for a predetermined time interval thereby achieving a phase step to substantially cover the phase distance between a measured phase relationship and said desired phase relationship. 
   
   
       9 . A phase locked loop (PLL), comprising:
 a frequency reference input for receiving a reference clock;   a controllable oscillator for generating a radio frequency (RF) clock;   a phase detector operational on said reference clock, said phase detector generating phase error samples in accordance therewith; and   a phase adjustor coupled to said controllable oscillator and said phase detector, said phase adjustor operative to receive said phase error samples and adjust the phase of said RF clock such that the impact of interference of said RF clock onto said reference clock is minimized.   
   
   
       10 . The PLL according to  claim 9 , wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the frequency of said controllable oscillator for a predetermined time interval. 
   
   
       11 . The PLL according to  claim 9 , further comprising a slicer operative to receive said reference clock and generate a digitized version thereof. 
   
   
       12 . The PLL according to  claim 9 , wherein said controllable oscillator is operative to generate said RF clock having a frequency in accordance with the frequency of said reference clock and the value of a frequency command word (FCW) input. 
   
   
       13 . The PLL according to  claim 12 , wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the value of said FCW for a predetermined time interval. 
   
   
       14 . The PLL according to  claim 9 , wherein the spectral content of induced jitter associated with said phase adjustment is shifted substantially outside a particular frequency band of interest, thereby minimizing its impact on a PLL output signal. 
   
   
       15 . The PLL according to  claim 9 , wherein said phase adjustor comprises:
 means for sweeping the phase relationship between said RF and frequency reference clock signals with a phase step;   means for assessing PLL performance by evaluation of said phase error samples; and   means for determining an optimum phase relationship and storing its location in a calibration table as a desired phase.   
   
   
       16 . The PLL according to  claim 9 , further comprising means for frequency modulation, wherein said RF clock interference causes modulation distortion. 
   
   
       17 . The PLL according to  claim 9 , wherein said phase adjustor is operative to adjust the phase of said RF clock in accordance with said phase error samples. 
   
   
       18 . The PLL according to  claim 9 , further coupled to a receiver, said receiver operative to downconvert said RF signal, and wherein said phase adjustor is operative to adjust the
 phase of said RF clock in accordance with measurements based on said down-converted RF signal.   
   
   
       19 . A single chip radio, comprising:
 a phase locked loop (PLL) comprising:   a frequency reference input for receiving a reference clock;   a controllable oscillator for generating a radio frequency (RF) clock;   a phase detector operational on said reference clock, said phase detector generating phase error samples in accordance therewith;   a phase adjustor coupled to said controllable oscillator and said phase detector, said phase adjustor operative to receive said phase error samples and adjust the phase of said RF clock such that the impact of interference of said RF clock onto said reference clock is minimized;   a transmitter coupled to said phase locked loop;   a receiver coupled to said phase locked loop; and   a baseband processor coupled to said transmitter and said receiver.   
   
   
       20 . The radio according to  claim 19 , wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the frequency of said controllable oscillator for a predetermined time interval. 
   
   
       21 . The PLL according to  claim 19 , wherein said controllable oscillator is operative to generate said RF clock having a frequency in accordance with the frequency of said reference clock and the value of a frequency command word (FCW) input. 
   
   
       22 . The PLL according to  claim 21 , wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the value of said FCW for a predetermined time interval. 
   
   
       23 . The PLL according to  claim 19 , wherein the spectral content of induced jitter associated with said phase adjustment is shifted substantially outside a particular frequency band of interest, thereby minimizing its impact on a PLL output signal. 
   
   
       24 . The PLL according to  claim 23 , wherein said frequency band of interest is substantially equal to the bandwidth of said PLL. 
   
   
       25 . The PLL according to  claim 19 , wherein said receiver is operative to downconvert said RF signal, and wherein said phase adjustor is operative to adjust the phase of said RF clock in accordance with measurements based on said down-converted RF signal.