Method and apparatus for universal program controlled bus architecture

Abstract

An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

1 . An integrated circuit, comprising:
 a programmable logic array comprising:
 a plurality of logic cells; and 
 programmable interconnections to receive digital input signals and to perform logical functions to transmit digital output signals; 
   a megacell comprising a plurality of functional blocks receiving digital inputs and transmitting digital outputs, wherein the megacell does not exclusively perform a memory function; and   a programmable interconnections subsystem to provide communication between the programmable logic array and the megacell.   
   
   
       2 . The integrated circuit as set forth in  claim 1 , wherein the megacell is implemented using programmed metal masks. 
   
   
       3 . The integrated circuit as set forth in  claim 1 , wherein the megacell is implemented using customized masks. 
   
   
       4 . A method, comprising:
 performing a processing function by a megacell; and   communicating digital signals between the megacell and a programmable logic array using a programmable interconnection subsystem.   
   
   
       5 . The method of  claim 4 , further comprising selecting, within the programmable interconnection subsystem, one of the digital signals using tri-statable logic control for at least one of input to or output from the megacell. 
   
   
       6 . The method of  claim 4 , further comprising selecting, within the programmable interconnection subsystem, one of the digital signals using tri-statable logic control for at least one of input to or output from the programmable logic array. 
   
   
       7 . The method of  claim 4 , further comprising programming the programmable interconnection subsystem to enable the communicating of the digital signals. 
   
   
       8 . The method of  claim 6 , further comprising providing a tri-state to the logic control in the programmable interconnection subsystem to enable the communicating.