Semiconductor device having high-voltage transistor and PIP capacitor and method for fabricating the same

Abstract

A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a substrate having a high-voltage transistor area and a PIP capacitor area, an extended drain region disposed in the high-voltage transistor area and separated from a source region, an impurity region formed in an upper portion of the extended drain region, and a drain region formed on a surface of the substrate and disposed within the impurity region.

1 . A semiconductor device, comprising:
 a substrate having a high-voltage transistor area and a polysilicon-insulator-polysilicon (PIP) capacitor area;   an extended drain region disposed in the high-voltage transistor area, wherein the extended drain region is separated from a source region;   an impurity region formed in an upper portion of said extended drain region; and   a drain region formed on a surface of said substrate and disposed within said impurity region.   
   
   
       2 . The semiconductor device of  claim 1 , further comprising:
 a gate formed on said substrate to be disposed between said extended drain region and the source region; and   a PIP capacitor formed in the PIP capacitor area.   
   
   
       3 . The semiconductor device of  claim 2 , wherein said gate is a gate stack formed by sequentially stacking a gate insulating layer pattern and a gate conductive layer pattern on a surface of said substrate. 
   
   
       4 . The semiconductor device of  claim 2 , wherein said PIP capacitor comprises a structure formed by sequentially stacking a first electrode layer pattern, a dielectric layer pattern, and a second electrode layer pattern. 
   
   
       5 . The semiconductor device of  claim 1 , wherein said impurity region and said extended drain region have the same conductivity. 
   
   
       6 . The semiconductor device of  claim 1 , wherein said impurity region and said the extended drain region have dissimilar impurity densities. 
   
   
       7 . The semiconductor device of  claim 1 , wherein said impurity region has a first impurity density, wherein said extended drain region has a second impurity density, and wherein the first impurity density is greater than the second impurity density. 
   
   
       8 . The semiconductor device of  claim 1 , wherein the impurity region is doped with phosphorus oxychloride. 
   
   
       9 . A semiconductor device, comprising:
 a substrate having a high-voltage transistor area and a polysilicon-insulator-polysilicon (PIP) capacitor area;   a source region and an extended drain region separately formed in the high-voltage transistor area;   an impurity region provided to an upper part within the extended drain region;   a drain region within the impurity region;   a gate stack disposed between the source region and the extended drain region; and   a PIP capacitor having a first electrode layer pattern, a dielectric layer pattern, and a second electrode layer pattern sequentially stacked in the PIP capacitor area.   
   
   
       10 - 13 . (canceled)