Methods of fabricating integrated circuit devices including strained channel regions and related devices

Abstract

A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.

1 . An integrated circuit device, comprising:
 a substrate including source/drain regions therein and a channel region therebetween, the source/drain regions comprising an epitaxially grown material configured to form a heterojunction with the substrate and to induce a net compressive strain or a net tensile strain on the channel region; and   a gate pattern on a surface of the substrate between the source/drain regions and adjacent the channel region.   
   
   
       2 . The device of  claim 1 , wherein the substrate comprises silicon, and wherein the epitaxially grown material comprises silicon germanium and/or germanium configured to induce the net compressive strain. 
   
   
       3 . The device of  claim 1 , wherein the substrate comprises silicon, and wherein the epitaxially grown material comprises silicon carbide configured to induce the net tensile strain. 
   
   
       4 . The device of  claim 1 , further comprising:
 an insulating layer extending between edges of the source/drain regions and the substrate.   
   
   
       5 . An integrated circuit device, comprising:
 a semiconductor substrate including a PMOS region and an NMOS region therein;   first and second gate patterns on surfaces of the substrate in the PMOS and NMOS regions, respectively;   p-type source/drain regions on opposite sides of the first gate pattern in the PMOS region defining a first channel region in portions of the substrate therebetween adjacent the first gate pattern, the p-type source/drain regions comprising a first epitaxially grown material configured to exert a net compressive stress on the first channel region; and   n-type source/drain regions on opposite sides of the second gate pattern in the NMOS region defining a second channel region in portions of the substrate therebetween adjacent the second gate pattern, the n-type source/drain regions comprising a second epitaxially grown material configured to exert a net tensile stress on the second channel region.   
   
   
       6 . The device of  claim 5 , wherein the semiconductor substrate comprises silicon and wherein the first epitaxially grown material comprises silicon germanium (SiGe) and/or germanium (Ge). 
   
   
       7 . The device of  claim 6 , wherein the semiconductor substrate includes silicon and wherein the second epitaxially grown material comprises silicon carbide (SiC). 
   
   
       8 . The device of  claim 5 , wherein a depth of the p-type and/or n-type source regions is less than a height of the first and/or second gate patterns. 
   
   
       9 . The device of  claim 5 , further comprising:
 an insulating layer extending between portions of the p-type and/or n-type source/drain regions and the substrate.   
   
   
       10 . The device of  claim 9 , further comprising:
 an isolation layer electrically separating the PMOS region and/or the NMOS region from an inactive region of the substrate,   wherein the insulating layer extends along portions of the p-type and/or n-type source/drain region to contact the isolation layer.   
   
   
       11 . The device of  claim 9 , wherein the insulating layer extends along sidewalls of the p-type and/or n-type source/drain regions to contact portions of the first and/or second channel regions. 
   
   
       12 . The device of  claim 11 , wherein the insulating layer extends along the sidewalls of the p-type and/or n-type source/drain regions such that the portion of the first channel region extends between the insulating layer and the first gate pattern and/or such that the portion of the second channel region extends between the insulating layer and the second gate pattern. 
   
   
       13 . A complementary metal-oxide-semiconductor (CMOS) device, comprising:
 a silicon substrate including a PMOS region and an NMOS region therein;   first and second gate patterns on surfaces of the substrate in the PMOS and NMOS regions, respectively;   silicon germanium source/drain regions on opposite sides of the first gate pattern in the PMOS region and configured to induce a net compressive strain on a first channel region in portions of the substrate therebetween; and   silicon carbide source/drain regions on opposite sides of the second gate pattern in the NMOS region and configured to induce a net tensile strain on a second channel region in portions of the substrate therebetween.   
   
   
       14 . A method of fabricating an integrated circuit device, the method comprising:
 forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions thereof, respectively;   epitaxially growing p-type source/drain regions on opposite sides of the first gate pattern in the PMOS region to exert a net compressive stress on a first channel region comprising a portion of the substrate therebetween adjacent the first gate pattern; and   epitaxially growing n-type source/drain regions on opposite sides of the second gate pattern in the NMOS region to exert a net tensile stress on a second channel region comprising a portion of the substrate therebetween adjacent the second gate pattern.   
   
   
       15 . The method of  claim 14 , wherein epitaxially growing the p-type and n-type source/drain regions comprises:
 etching the semiconductor substrate using the first and second gate patterns as etching masks to define trenches therein adjacent the first and second gate patterns on the opposite sides thereof;   epitaxially growing a first material in the trenches adjacent the first gate pattern to define the p-type source/drain regions, the first material being configured to generate the net compressive stress on the first channel region; and   epitaxially growing a second material in the trenches adjacent the second gate pattern to define the n-type source/drain regions, the second material being configured to generate the net tensile stress on the second channel region.   
   
   
       16 . The method of  claim 15 , further comprising the following prior to epitaxially growing the first and second materials:
 forming spacer patterns on sidewalls of the trenches extending adjacent to sidewalls of the first and second gate patterns;   forming an insulating layer on surfaces of the trenches exposed by the spacer pattern; and   removing the spacer patterns.   
   
   
       17 . The method of  claim 16 , wherein the forming the spacer patterns comprises:
 depositing a nitride layer on the sidewalls of the trenches using a chemical vapor deposition (CVD) process.   
   
   
       18 . The method of  claim 16 , wherein the forming the insulating layer comprises:
 oxidizing the exposed surfaces of the trenches.   
   
   
       19 . The method of  claim 16 , wherein the removing of the spacer pattern comprises:
 dipping the spacer patterns in a sulfur oxide solution; and   dipping the spacer patterns in a solution comprising ammonia (NH 4 OH), water (H 2 O), and/or deionized water.   
   
   
       20 . The method of  claim 15 , wherein the semiconductor substrate comprises silicon, and wherein epitaxially growing the first material comprises epitaxially growing silicon germanium (SiGe) and/or germanium (Ge). 
   
   
       21 . The method of  claim 15 , wherein the semiconductor substrate comprises silicon, and wherein epitaxially growing the second material comprises epitaxially growing silicon carbide (SiC). 
   
   
       22 . The method of  claim 15 , wherein etching the semiconductor substrate comprises:
 etching the substrate to define the trenches therein having a depth that is less than a height of the first and/or second gate patterns.   
   
   
       23 . The method of  claim 14 , wherein epitaxially growing the p-type and n-type source/drain regions comprises:
 selectively forming a first photoresist pattern on one of the PMOS region and the NMOS region; and then   epitaxially growing one of the p-type and the n-type source/drain regions on a corresponding one of the PMOS and NMOS regions that does not include the first photoresist pattern thereon.   
   
   
       24 . The method of  claim 23 , further comprising:
 forming a protection layer pattern on the epitaxially grown one of the p-type and n-type source/drain regions;   removing the first photoresist pattern;   selectively forming a second photoresist pattern on the corresponding one of the PMOS and NMOS regions including the one of the p-type and n-type source/drain regions;   epitaxially growing another one of the p-type and n-type source/drain regions on a corresponding one of the PMOS and NMOS regions that does not include the second photoresist pattern thereon; and   removing the second photoresist pattern.   
   
   
       25 . The method of  claim 24 , wherein the forming the protection layer pattern comprises:
 forming a silicon layer pattern; and   forming an oxide layer pattern on the silicon layer pattern.   
   
   
       26 . A method of fabricating an integrated circuit device, the method comprising:
 forming a gate pattern on a surface of a substrate; and   epitaxially growing source/drain regions on opposite sides of the gate pattern to form a heterojunction with the substrate and to induce a net compressive strain or a net tensile strain on a channel region therebetween comprising a portion of the substrate adjacent the gate pattern.   
   
   
       27 . The method of  claim 26 , wherein epitaxially growing the source/drain regions comprises:
 etching the substrate using the gate pattern as an etching mask to define trenches therein adjacent the gate patterns on the opposite sides thereof; and   epitaxially growing a material in the trenches adjacent the first gate pattern to define the source/drain regions, the material being configured to generate the net compressive strain or the net tensile strain on the channel region.   
   
   
       28 . The method of  claim 27 , wherein the substrate comprises silicon, and wherein the epitaxially grown material comprises silicon germanium and/or germanium configured to induce the net compressive strain. 
   
   
       29 . The method of  claim 27 , wherein the substrate comprises silicon, and wherein the epitaxially grown material comprises silicon carbide configured to induce the net tensile strain.