Electrostatic discharge protection device and method of fabricating the same

Abstract

An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

1 - 13 . (canceled) 
   
   
       14 . A method of fabricating an electrostatic discharge protection device, comprising:
 forming a p-well region at an upper portion of a substrate and an n-well region under the p-well region, wherein the n-well region extends vertically along a sidewall of the p-well region to define a junction between the p-well region and the n-well region at a surface of the substrate;   forming an n+ source and an n+ drain separated from each other by implanting impurities in the p-well region, wherein the n+ drain is formed to overlap the junction of the p-well region and the n-well region;   forming a p+ well pick-up by implanting impurities in the p-well region; and   forming an interconnection connected to each of the p+ well pick-up, the n+ source and the n+ drain, wherein the p+ well pick-up and the n+ source are connected to a ground terminal, and the n+ drain is connected to a circuit terminal.   
   
   
       15 . The method as claimed in  claim 14 , further comprising forming a device isolation layer in the substrate to define an active region, before forming the n-well region and the p-well region,
 wherein the active region includes the n-well region and the p-well region, and the n+ source, the p+ well pick-up and the n+ drain are formed in the active region.   
   
   
       16 . The method as claimed in  claim 14 , further comprising forming a device isolation layer in the substrate to define an active region, after forming the n-well region and the p-well region,
 wherein the active region includes the n-well region and the p-well region, and the n+ source, the p+ well pick up and the n+ drain are formed in the active region.   
   
   
       17 . The method as claimed in  claim 14 , wherein an interconnection connected to the n+ drain extends over a region between the n+ source and the n+ drain, such that an edge of the interconnection overlaps the n+ source. 
   
   
       18 . A method of fabricating an electrostatic discharge protection device connected to a circuit terminal and a ground terminal, comprising:
 forming a p-well region at an upper portion of a substrate and an n-well region under the p-well region, wherein the n-well region extends vertically along a sidewall of the p-well region to define a junction of the p-well region and the n-well region at a surface of the substrate;   forming a gate electrode on the p-well region;   implanting impurities in the substrate at either side of the gate electrode to form an n+ source and an n+ drain, wherein the n+ drain is formed to overlap a junction between the p-well region and the n-well region;   implanting impurities in the p-well region to form a p+ well pick-up; and   forming an interconnection connecting each of the p+ well pick-up, the gate electrode, the n+ source and the n+ drain,   wherein the p+ well pick-up and the n+ source are connected to the ground terminal, and the n+ drain is connected to the circuit terminal.   
   
   
       19 . The method as claimed in  claim 18 , further comprising forming a device isolation layer in the substrate to define an active region, before forming the n-well region and the p-well region,
 wherein the active region includes the n-well region and the p-well region, the gate electrode crosses over the p-well region in the active region, and   wherein the active region at one side of the gate electrode includes the p-well region and the active region at the other side of the gate electrode includes the p-well region and the n-well region.   
   
   
       20 . The method as claimed in  claim 18 , further comprising forming a device isolation layer in the substrate to define an active region, after forming the n-well region and the p-well region,
 wherein the active region includes the n-well region and the p-well region, and   wherein the gate electrode crosses over the p-well region in the active region, and the active region at one side of the gate electrode is the p-well region and the active region at the other side includes the p-well region and the n-well region.   
   
   
       21 . The method as claimed in  claim 18 , wherein the gate electrode is connected to a ground terminal. 
   
   
       22 . A method of fabricating an electrostatic discharge protection device, comprising:
 forming an n-well in a substrate;   forming a p-well on the n-well;   forming an NMOS transistor on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain; and   forming a grounded p+ well pick-up in the p-well,   wherein the n-well is directly connected to the n+ drain of the NMOS transistor and the n+ source is grounded.   
   
   
       23 . The method as claimed in  claim 22 , wherein the gate electrode is grounded. 
   
   
       24 . The method as claimed in  claim 22 , wherein the gate electrode is electrically connected to the n+ drain. 
   
   
       25 . The method as claimed in  claim 22 , wherein an impurity concentration of the n+ drain is higher than that of the n+ source. 
   
   
       26 . The method as claimed in  claim 22 , wherein the n-well extends vertically under the n+ drain and contacts the n+ drain. 
   
   
       27 . The method as claimed in  claim 22 ,
 wherein the n-well extends vertically to form a junction with the p-well, and   wherein a junction of the n-well and the p-well overlaps the n+ drain.   
   
   
       28 . The method as claimed in  claim 17 , wherein the n+ source, the gate electrode and the p+ well pick-up are connected to the interconnection in parallel. 
   
   
       29 . The method as claimed in  claim 14 , wherein an impurity concentration of the n+ drain is higher than that of the n+ source.