Techniques for Patterning Features in Semiconductor Devices

Abstract

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

1 . A lithographic structure, the lithographic structure comprising an antireflective material having a feature patterned therein, the feature having at least one reduced critical dimension. 
   
   
       2 . The lithographic structure of  claim 1 , wherein the antireflective material is deposited on a substrate, the substrate having a feature patterned therein, the feature having at least one reduced critical dimension. 
   
   
       3 . The lithographic structure of  claim 1 , wherein the antireflective material comprises one or more inorganic moieties. 
   
   
       4 . The lithographic structure of  claim 1 , wherein the antireflective material has the structural formula M:carbon:hydrogen:X, wherein M comprises a metal and X comprises an inorganic element. 
   
   
       5 . The lithographic structure of  claim 4 , wherein M comprises a metal selected from the group consisting of silicon, titanium, germanium, iron, boron, tin and combinations comprising at least one of the foregoing metals. 
   
   
       6 . The lithographic structure of  claim 4 , wherein X comprises an inorganic element selected from the group consisting of oxygen, hydrogen, nitrogen and combinations comprising at least one of the foregoing inorganic elements. 
   
   
       7 . The lithographic structure of  claim 1 , wherein the antireflective material has the structural formula silicon:carbon:hydrogen:oxygen. 
   
   
       8 . The lithographic structure of  claim 1 , wherein the antireflective material comprises a tunable etch resistant antireflective coating. 
   
   
       9 . The lithographic structure of  claim 1 , wherein the antireflective material is deposited on a substrate using spin on processing. 
   
   
       10 . The lithographic structure of  claim 1 , wherein the antireflective material is deposited on a substrate using plasma enhanced chemical vapor deposition. 
   
   
       11 . The lithographic structure of  claim 1 , wherein the feature comprises a feature selected from the group consisting of contact holes, via patterns, lines, spaces, ovals and combinations comprising at least one of the foregoing features. 
   
   
       12 . The lithographic structure of  claim 1 , wherein the critical dimensions of any given feature is reduced by up to about 50 nanometers. 
   
   
       13 . The lithographic structure of  claim 1 , wherein the critical dimensions of any given feature is reduced by up to about 80 nanometers. 
   
   
       14 . The lithographic structure of  claim 1 , wherein the antireflective material is deposited on a substrate comprising a dielectric material. 
   
   
       15 . The method of  claim 1 , wherein the antireflective material is deposited on a substrate comprising a low-k dielectric material. 
   
   
       16 . The lithographic structure of  claim 1 , wherein the antireflective material is deposited on a substrate comprising an oxide material selected from the group consisting of fluorosilicate glass, borosilicate glass, borophosphorosilicate glass and combinations comprising at least one of the foregoing oxide materials.