Power control structure for managing a plurality of voltage islands
Abstract
A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied to predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.
Claims
exact text as granted — not AI-modified1 . A power control structure for managing a plurality of voltage islands of a functional chip comprising:
a substrate carrier; a supply control and partition chip being positioned between said substrate carrier and the functional chip including a plurality of voltage islands; said supply control and partition chip including a plurality of first electrical connections to the functional chip including the plurality of voltage islands; said supply control and partition chip including a plurality of second electrical connections to the substrate carrier; and said supply control and partition chip selectively switching on and off power applied to predefined ones of the first electrical connections to the functional chip.
2 . The power control structure as recited in claim 1 wherein said supply control and partition chip selectively adjusts a local voltage coupled by a set of predetermined ones of said first electrical connections to said functional chip.
3 . The power control structure as recited in claim 1 wherein said supply control and partition chip includes predefined ones of said first electrical connections being connected to respective ones of said second electrical connections for coupling signals between said substrate carrier and the functional chip.
4 . The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip has a smaller pitch than said plurality of second electrical connections to said substrate carrier.
5 . The power control structure as recited in claim 1 wherein said supply control and partition chip is positioned between said substrate carrier and a pair of the functional chips, wherein said supply control and partition chip including a plurality of first electrical connections to each of the functional chips.
6 . The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip include a pattern of solder bumps.
7 . The power control structure as recited in claim 6 wherein said pattern of solder bumps is formed by controlled collapse chip connection (C4).
8 . The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip includes a ball grid array (BGA).
9 . The power control structure as recited in claim 1 wherein said plurality of second electrical connections to said substrate carrier includes a pattern of solder bumps.
10 . The power control structure as recited in claim 1 wherein said plurality of second electrical connections to said substrate carrier includes ball grid array (BGA).
11 . The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip include a coaxial signal structure.
12 . The power control structure as recited in claim 11 wherein said coaxial signal structure includes a predefined signal first electrical connection coupling a signal; and a group of predefined first electrical connections surrounding said predefined signal first electrical connection coupled to ground potential.
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