Chip package and process thereof

Abstract

The chip package and the process thereof are disclosed. The chip package comprises a chip and a rigid cover. The chip has a plurality of bond pads formed thereon. The rigid cover is located on the chip and has a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.

1 . A chip package, comprising:
 a chip having a plurality of bond pads formed thereon; and   a rigid cover located on the chip and having a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.   
   
   
       2 . The chip package of  claim 1  further comprising an adhesive layer disposed between the chip and the rigid cover, wherein the rigid cover is adhered to the chip via the adhesive layer. 
   
   
       3 . The chip package of  claim 1  further comprising a plurality of contacts electrically connected to the bond pads respectively. 
   
   
       4 . The chip package of  claim 3 , wherein the contacts include conductive bumps. 
   
   
       5 . The chip package of  claim 3 , wherein the contacts are connected to the PCB. 
   
   
       6 . The chip package of  claim 3 , wherein the heights of the contacts relative to a top surface of the chip are larger than the height of the rigid cover to the top surface. 
   
   
       7 . The chip package of  claim 1 , wherein the chip includes a redistribution layer on the chip to form the bond pads. 
   
   
       8 . The chip package of  claim 1 , wherein the material of the rigid cover includes a conducting material, an insulating material, or a transparent material. 
   
   
       9 . The chip package of  claim 1 , wherein the bond pads are disposed on the chip as an array. 
   
   
       10 . The chip package of  claim 1 , wherein the bond pads are disposed in an interior region of the chip.