Method and structure for integrating mim capacitors within dual damascene processing techniques

Abstract

A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

1 . A metal-insulator-metal (MIM) capacitor structure, comprising:
 a lower interlevel dielectric (ILD) layer having a lower capacitor electrode formed therein;   a first dielectric capping layer formed on said lower ILD layer and said lower capacitor electrode;   an upper ILD layer formed over said first dielectric capping layer; and   an upper capacitor electrode structure formed in said upper ILD layer and in contact with said first dielectric capping layer.   
   
   
       2 . The structure of  claim 1 , wherein:
 said upper and lower ILD layers have a dielectric constant of about 2.0 to about 3.0; and   said first dielectric capping layer has a dielectric constant of about 3.0 to about 7.0.   
   
   
       3 . A metal-insulator-metal (MIM) capacitor structure, comprising:
 a lower interlevel dielectric (ILD) layer having a lower capacitor electrode formed therein;   a selective metal cap formed on said lower capacitor electrode;   a MIM capacitor dielectric structure formed over said selective metal cap;   an upper ILD layer formed over said selective metal cap and said MIM capacitor dielectric structure; and   an upper capacitor electrode structure formed in said upper ILD layer and in contact with said MIM capacitor dielectric structure.   
   
   
       4 . The structure of  claim 3 , wherein said MIM capacitor dielectric structure comprises one of: HfO 2 , ZrO 2 , TaO 2  and Si 3 N 4 . 
   
   
       5 . The structure of  claim 3 , wherein:
 said upper and lower ILD layers have a dielectric constant of about 2.0 to about 3.0; and   said MIM capacitor dielectric structure has a dielectric constant of greater than about 7.0.   
   
   
       6 . The structure of  claim 3 , further comprising a dielectric capping layer formed between said selective metal cap and said upper ILD layer. 
   
   
       7 . A metal-insulator-metal (MIM) capacitor structure, comprising:
 a lower interlevel dielectric (ILD) layer having a lower capacitor electrode formed therein;   a first dielectric capping layer formed on said lower ILD layer and said lower capacitor electrode;   an upper ILD layer formed over said first dielectric capping layer; and   an upper capacitor electrode structure formed in said upper ILD, said upper capacitor electrode structure further comprising: a plurality of via structures filled with an electrically conductive material, a bottom end of the via structures in contact with said first dielectric capping layer; and a conductive line structure in contact with a top end of the via structures.   
   
   
       8 . The structure of  claim 7 , wherein:
 said upper and lower ILD layers have a dielectric constant of about 2.0 to about 3.0; and   said first dielectric capping layer has a dielectric constant of about 3.0 to about 7.0.