Semiconductor device and manufacturing method

Abstract

A semiconductor device has a Si substrate, a gate insulating film over the Si substrate, a gate electrode over the gate insulating film, a source region and a drain region in the Si substrate, wherein each of the source region and the drain region includes a first Si layer including Ge, an interlayer over the first Si layer, and a second Si layer including Ge over the interlayer, wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.

1 . A semiconductor device comprising:
 a Si substrate;   a gate insulating film over the Si substrate;   a gate electrode over the gate insulating film;   a source region and a drain region in the Si substrate;   wherein each of the source region and the drain region includes a first Si layer including Ge, an interlayer over the first Si layer, and a second Si layer including Ge over the interlayer, wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first Si layer is lattice matching to the Si substrate, the interlayer is lattice matching to the first Si layer, the second Si layer is lattice matching to the interlayer. 
     
     
         3 . The semiconductor device according to  claim 1  further comprising a recess in the Si substrate, wherein the first Si layer, the interlayer, and the second Si layer are formed in the recess. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the Ge concentration of the first Si layer and the Ge concentration of the second Si layer is in the range from 20% to 40% in atomic %. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein each of the source region and the drain region includes B as p-type impurity, and a concentration of B is in the range from 1×10 19  cm −3  to 1×10 21  cm −3 . 
     
     
         6 . A semiconductor device comprising:
 a Si substrate;   a gate insulating film over the Si substrate;   a gate electrode over the gate insulating film;   a source region and a drain region in the Si substrate;   wherein the each of the source region and the drain region includes a first Si layer including C over the Si substrate, an interlayer over the first Si layer, and a second Si layer including C over the interlayer, wherein the interlayer is composed of Si or Si including C, and a C concentration of the interlayer is less than a C concentration of the first Si layer and a C concentration of the second Si layer.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the first Si layer is lattice matching to the Si substrate, the interlayer is lattice matching to the first Si layer, the second Si layer is lattice matching to the interlayer. 
     
     
         8 . The semiconductor device according to  claim 6 , an interface between the first Si layer and the Si substrate is lower than the surface of the Si substrate. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein the C concentration of the first Si layer and the C concentration of the second Si layer is in the range from 1% to 2% in atomic %. 
     
     
         10 . The semiconductor device according to  claim 6 , wherein each the source and the drain region includes P or As as n-type impurity, and the concentration of P or As is in the range from 1×10 19  cm −3  to 1×10 21  cm −3 . 
     
     
         11 . A method of manufacturing a semiconductor device comprising:
 forming a gate insulating film and a gate electrode over a Si substrate;   forming a recess in the Si substrate at both sides of the gate electrode;   forming a first Si layer including Ge in the recess;   forming an interlayer over the first Si layer;   forming a second Si layer including Ge over the interlayer;   wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.   
     
     
         12 . The method of manufacturing the semiconductor device according to  claim 11 , wherein the first Si layer is formed by epitaxial growth, the interlayer is formed by epitaxial growth, and the second Si layer is formed by epitaxial growth. 
     
     
         13 . The method of manufacturing the semiconductor device according to  claim 11 , wherein a thickness of each of the first Si layer, and the second Si layer is equal to or less than a critical film thickness. 
     
     
         14 . The method of manufacturing the semiconductor device according to  claim 11 , wherein the Ge concentration of the first Si layer and the Ge concentration of the second Si layer is in a range from 20% to 40% in atomic %. 
     
     
         15 . The method of manufacturing the semiconductor device according to  claim 11 , wherein each of the source and the drain region includes B as p-type impurity, and the concentration of B is in the range from 1×10 19  cm −3  to 1×10 21  cm −3 . 
     
     
         16 . A method of manufacturing a semiconductor device comprising:
 forming a gate insulating film and a gate electrode over a Si substrate;   forming a recess in the Si substrate at both sides of the gate electrode;   forming a first Si layer including C in the recess;   forming a interlayer over the first Si layer;   forming a second Si layer including C over the interlayer;   wherein the interlayer is composed of Si or Si including C, and a C concentration of the interlayer is less than a C concentration of the first Si layer and a C concentration of the second Si layer.   
     
     
         17 . The method of manufacturing the semiconductor device according to  claim 16 , wherein the first Si layer is formed by epitaxial growth, the interlayer is formed by epitaxial growth, and the second Si layer is formed by epitaxial growth. 
     
     
         18 . The method of manufacturing the semiconductor device according to  claim 16 , wherein the thickness of each of the first Si layer, and the second Si layer is equal to or less than a critical film thickness. 
     
     
         19 . The method of manufacturing the semiconductor device according to  claim 16 , wherein the C concentration of the first Si layer and the C concentration of the second Si layer is in the range from 1% to 2% in atomic %. 
     
     
         20 . The method of manufacturing the semiconductor device according to  claim 16 , wherein each of the source and the drain region includes P or As as n-type impurity, and the concentration of P or As is in the range from 1×10 19  cm −3  to 1×10 21  cm −3 .