Interposer for connecting plurality of chips and method for manufacturing the same

Abstract

The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.

1 . An interposer for connecting a plurality of chips, the interposer comprising:
 a connective substrate having a first surface and a second surface;   at least a first chip disposed on the first surface, wherein the first chip is a flip-chip;   at least a second chip disposed on the second surface, wherein the second chip is a flip-chip; and   at least a through via positioned in the connective substrate to connect the first surface and the second surface.   
     
     
         2 . The interposer of  claim 1 , wherein the first surface further comprises:
 a plurality of first dielectric layers disposed on the first surface;   a plurality of first interconnections respectively embedded through the plurality of first dielectric layers;   a plurality of first contact pads respectively disposed on a surface of the plurality of first dielectric layers, the plurality of first contact pads electrically connected to the plurality of first interconnections respectively;   a plurality of first under bump metallurgies respectively disposed on a surface of the plurality of first contact pads; and   a plurality of first bumps sandwiched between the first chip and the plurality of first under bump metallurgies for electrical connectivity between the first chip and the first surface.   
     
     
         3 . The interposer of  claim 1 , wherein the second surface further comprises:
 a plurality of second dielectric layers disposed on the first surface;   a plurality of second interconnections respectively embedded through the plurality of second dielectric layers;   a plurality of second contact pads respectively disposed on a surface of the plurality of second dielectric layers, the plurality of second contact pads electrically connected to the plurality of second interconnections respectively;   a plurality of second under bump metallurgies respectively disposed on a surface of the plurality of second contact pads; and   a plurality of second bumps sandwiched between the second chip and the plurality of second under bump metallurgies for electrical connectivity between the second chip and the second surface.   
     
     
         4 . The interposer of  claim 2 , wherein the first interconnections comprise AlCu alloy, Cu, Al, or Au. 
     
     
         5 . The interposer of  claim 3 , wherein the second interconnections comprise AlCu alloy, Cu, Al, or Au. 
     
     
         6 . The interposer of  claim 1 , further comprising at least a third chip electrically connected to the first surface or the second surface of the connective substrate by wires. 
     
     
         7 . The interposer of  claim 2 , wherein a critical dimension of each first interconnection is greater than 10 micrometers. 
     
     
         8 . The interposer of  claim 3 , wherein a critical dimension of each second interconnection is greater than 10 micrometers. 
     
     
         9 . A method of forming an interposer, comprising:
 providing a connective substrate having a first surface and a second surface, the connective substrate further comprising at least a first dielectric layer, at least a first interconnection and at least a first contact pad disposed on the first surface;   providing an adhesive layer to bond the first surface to a wafer carrier;   forming at least a through hole on the second surface of the connective substrate;   forming a conductive layer to fill the through hole and forming a through via between the first surface and the second surface;   forming at least a second dielectric layer, at least a second interconnection, and at least a second contact pad on the second surface of the connective substrate, wherein the through via electrically connects the second interconnection and the second contact pad; and   separating the first surface and the wafer carrier.   
     
     
         10 . The method of  claim 9 , further comprising:
 forming a stress buffer layer on the second surface of the connective substrate after the first surface is bonded to the wafer carrier.   
     
     
         11 . The method of  claim 9 , further comprising
 forming a protective layer covering the second dielectric layer and the second interconnection and exposing the second contact pad, after the second dielectric layer, the second interconnection, and the second contact pad are formed on the second surface of the connective substrate.   
     
     
         12 . The method of  claim 9 , wherein a thinning process is optionally performed on the second surface of the connective substrate after the first surface of the connective substrate is bonded to the wafer carrier. 
     
     
         13 . The method of  claim 9 , wherein forming the through via further comprises:
 performing an electroplating process to form the conductive layer covering the second surface and filling the through hole; and   performing a planarization process to remove a part of the conductive layer on the second surface of the connective substrate and form the through via.   
     
     
         14 . An interposer for connecting chips, comprising:
 a connective substrate having a first surface and a second surface;   at least a first chip disposed on the first surface and electrically connected to the first surface; and   at least a second chip disposed on the second surface and electrically connected to the second surface.   
     
     
         15 . The interposer of  claim 14 , further comprising at least a through via disposed in the connective substrate for electrical connectivity between the first surface and the second surface. 
     
     
         16 . The interposer of  claim 14 , further comprising at least a third chip electrically connected to the first surface or the second surface by wires.