Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same

Abstract

An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.

1 - 23 . (canceled) 
   
   
       24 . A computer implemented method for designing an integrated circuit (IC) floorplan power supply net, the method comprising:
 determining a IC floorplan power supply net for a metal layer of an interconnect structure of an IC, wherein
 the metal layer is exclusively reserved for the IC floorplan power supply net, 
 the IC floorplan includes at least one power consuming entity to be electrically coupled with the IC floorplan power supply net, a power consuming entity constituting an exempt area, 
 the power supply net occupies all of the designated metal layer except exempt areas of the IC floorplan; and 
   generating the IC floorplan power supply net.   
   
   
       25 . The method of  claim 24  further comprising:
 outputting the generated IC floorplan power supply net information.   
   
   
       26 . The method of  claim 24  further comprising:
 dividing the power supply net into non-slotted regions and slot regions.   
   
   
       27 . The method of  claim 24  further comprising:
 provisioning a save ring around a power consuming entity, the save ring including non-slotted save ring vertices at the junctures of horizontal save ring regions and vertical save ring regions respectively adjacent the power consuming entity's horizontal edges and vertical edges.   
   
   
       28 . The method of to  claim 24  wherein a second metal layer of an interconnect structure of the IC is exclusively reserved for the power supply net, wherein one reserved metal layer is reserved for a power net and the other reserved metal layer is reserved for a ground net. 
   
   
       29 . The method of  claim 24  further comprising:
 applying a minus union algorithm to a power supply net to minimize the number of power supply net rectangles uniquely describing its shape   
   
   
       30 . The method of  claim 29  wherein the minus union algorithm comprises:
 placing a grid over a power supply net, the grid including horizontal and vertical grid lines at all of the transitions between non-slotted regions, horizontal save ring regions, and vertical save ring regions;   merging contiguous grid rectangles of a power supply net bounded by a pair of adjacent horizontal grid lines to form landscape power supply net rectangles defined as having an aspect ratio greater than 1, wherein an aspect ratio is defined as the width of a power supply net rectangle divided by its height; and   merging contiguous grid rectangles bounded by a pair of adjacent vertical grid lines, without violating the landscape power supply net rectangles, to form portrait power supply net rectangles defined as having an aspect ratio less than 1.   
   
   
       31 . A machine readable medium having executable instructions to cause a machine to perform a method for designing an integrated circuit (IC) floorplan power supply net, the method comprising:
 determining a IC floorplan power supply net for a metal layer of an interconnect structure of an IC, wherein
 the metal layer is exclusively reserved for the IC floorplan power supply net, 
 the IC floorplan includes at least one power consuming entity to be electrically coupled with the IC floorplan power supply net, a power consuming entity constituting an exempt area, 
 the power supply net occupies all of the designated metal layer except exempt areas of the IC floorplan; and 
   generating the IC floorplan power supply net.   
   
   
       32 . The machine readable medium of  claim 31  further comprising:
 outputting the generated IC floorplan power supply net information.   
   
   
       33 . The machine readable medium of  claim 31  further comprising:
 dividing the power supply net into non-slotted regions and slot regions.   
   
   
       34 . The machine readable medium of  claim 31  further comprising:
 provisioning a save ring around a power consuming entity, the save ring including non-slotted save ring vertices at the junctures of horizontal save ring regions and vertical save ring regions respectively adjacent the power consuming entity's horizontal edges and vertical edges.   
   
   
       35 . The machine readable medium of to  claim 31  wherein a second metal layer of an interconnect structure of the IC is exclusively reserved for the power supply net, wherein one reserved metal layer is reserved for a power net and the other reserved metal layer is reserved for a ground net. 
   
   
       36 . The machine readable medium of  claim 31  further comprising:
 applying a minus union algorithm to a power supply net to minimize the number of power supply net rectangles uniquely describing its shape   
   
   
       37 . The machine readable medium of  claim 36  wherein the minus union algorithm comprises:
 placing a grid over a power supply net, the grid including horizontal and vertical grid lines at all of the transitions between non-slotted regions, horizontal save ring regions, and vertical save ring regions;   merging contiguous grid rectangles of a power supply net bounded by a pair of adjacent horizontal grid lines to form landscape power supply net rectangles defined as having an aspect ratio greater than 1, wherein an aspect ratio is defined as the width of a power supply net rectangle divided by its height; and   merging contiguous grid rectangles bounded by a pair of adjacent vertical grid lines, without violating the landscape power supply net rectangles, to form portrait power supply net rectangles defined as having an aspect ratio less than 1.   
   
   
       38 . An apparatus comprising:
 a processor; and   a memory coupled to the processor to store instructions to cause the processor to perform a method comprising:
 determining a IC floorplan power supply net for a metal layer of an interconnect structure of an IC, wherein
 the metal layer is exclusively reserved for the IC floorplan power supply net, 
 the IC floorplan includes at least one power consuming entity to be electrically coupled with the IC floorplan power supply net, a power consuming entity constituting an exempt area, 
 the power supply net occupies all of the designated metal layer except exempt areas of the IC floorplan; and 
 
 generating the IC floorplan power supply net. 
   
   
   
       39 . The apparatus of  claim 38  wherein the processor performs a method further comprising:
 outputting the generated IC floorplan power supply net information.   
   
   
       40 . The apparatus of  claim 38  wherein the processor performs a method further comprising:
 dividing the power supply net into non-slotted regions and slot regions.   
   
   
       41 . The apparatus of  claim 38  wherein the processor performs a method further comprising:
 provisioning a save ring around a power consuming entity, the save ring including non-slotted save ring vertices at the junctures of horizontal save ring regions and vertical save ring regions respectively adjacent the power consuming entity's horizontal edges and vertical edges.   
   
   
       42 . The apparatus of  claim 38  wherein a second metal layer of an interconnect structure of the IC is exclusively reserved for the power supply net, wherein one reserved metal layer is reserved for a power net and the other reserved metal layer is reserved for a ground net. 
   
   
       43 . The apparatus of  claim 38  wherein the processor performs a method further comprising:
 applying a minus union algorithm to a power supply net to minimize the number of power supply net rectangles uniquely describing its shape   
   
   
       44 . The apparatus of  claim 43  wherein the minus union algorithm comprises:
 placing a grid over a power supply net, the grid including horizontal and vertical grid lines at all of the transitions between non-slotted regions, horizontal save ring regions, and vertical save ring regions;   merging contiguous grid rectangles of a power supply net bounded by a pair of adjacent horizontal grid lines to form landscape power supply net rectangles defined as having an aspect ratio greater than 1, wherein an aspect ratio is defined as the width of a power supply net rectangle divided by its height; and   merging contiguous grid rectangles bounded by a pair of adjacent vertical grid lines, without violating the landscape power supply net rectangles, to form portrait power supply net rectangles defined as having an aspect ratio less than 1.