Method and apparatus for controlling timing of state transition of serial data line in 12c controller

Abstract

A method and apparatus for controlling the timing of a state transition of a serial data line (SDA) in an I2C controller are provided. The apparatus includes a processor, a serial clock line (SCL) edge detector, a counter, and an SDA generator. The processor controls an I2C controller. The SCL edge detector detects an edge of a clock signal of an SCL. The counter counts a hold time of the state transition of the SDA if a falling edge of the clock signal of the SCL is detected by the SCL edge detector. The SDA generator transits the state of the SDA if the count of the hold time is finished. Therefore, a malfunction in an I2C communication can be prevented without using a compensation circuit requiring a lot of time and cost.

1 . An apparatus which controls the timing of a state transition of a serial data line (SDA), the apparatus comprising:
 a serial clock line SCL edge detector which detects an edge of a clock signal of an SCL;   a counter which counts a hold time of the state transition of the SDA when a falling edge of the clock signal of the SCL is detected by the SCL edge detector;   an SDA generator which transits a state of the SDA if the count of the hold time is finished; and   a processor which interfaces the SCL edge detector, the counter, and the SDA generator.   
   
   
       2 . The apparatus of  claim 1 , further comprising an Intelligent Interface Controller (I2C) slave interface which sets a hold time of the counter by receiving a hold time from a central processing unit (CPU). 
   
   
       3 . The apparatus of  claim 1 , wherein the processor determines if the state transition of the SDA is for a purpose of transmitting a start signal of data transmission or an end signal of the data transmission, or for a purpose of actual data transmission. 
   
   
       4 . The apparatus of  claim 3 , wherein the SDA generator changes the state of the SDA without counting the hold time if the state transition of the SDA is for the purpose of transmitting the start signal of the data transmission or the end signal of the data transmission. 
   
   
       5 . The apparatus of  claim 1 , wherein the counter counts in synchronization with a system clock signal received from outside of the I2C controller. 
   
   
       6 . The apparatus of  claim 1 , wherein the counter performs down-counting from the hold time to 0. 
   
   
       7 . The apparatus of  claim 1 , wherein the counter initializes the hold time if a rising edge of the clock signal is detected by the SCL edge detector. 
   
   
       8 . The apparatus of  claim 2 , wherein the I2C slave interface comprises a register for hold time enable setting. 
   
   
       9 . The apparatus of  claim 1 , wherein the counter is set to a different hold time according to a transmission speed of a slave device. 
   
   
       10 . The apparatus of  claim 1 , wherein the hold time is smaller than a time interval between a rising edge of the clock signal and the state transition of the SDA. 
   
   
       11 . A method of controlling the timing of a state transition of a serial data line (SDA) in an I2C controller, the method comprising:
 detecting a falling edge of a clock signal of a serial clock line (SCL);   counting a hold time of the state transition of the SDA if the falling edge of the clock signal of the SCL is detected; and   transmitting the state of the SDA if the count of the hold time is finished.   
   
   
       12 . The method of  claim 11 , further comprising setting the hold time by receiving a hold time of the state transition of the SDA from a central processing unit (CPU). 
   
   
       13 . The method of  claim 11 , further comprising determining if the state transition of the SDA is for a purpose of transmitting a start signal of data transmission or an end signal of the data transmission, or for a purpose of transmitting actual data. 
   
   
       14 . The method of  claim 13 , further comprising changing the state of the SDA without counting the hold time if the state transition of the SDA is for the purpose of transmitting the start signal of the data transmission or the end signal of the data transmission. 
   
   
       15 . The method of  claim 11 , wherein the counting of the hold time comprises counting in synchronization with a system clock signal received from outside of the I2C controller. 
   
   
       16 . The method of  claim 11 , wherein the counting of the hold time comprises performing down counting from the hold time to 0. 
   
   
       17 . The method of  claim 11 , further comprising:
 detecting a rising edge of the clock signal of the SCL; and   initializing the hold time if the rising edge of the clock signal is detected.   
   
   
       18 . The method of  claim 11 , further comprising determining if a hold time enable setting is set. 
   
   
       19 . The method of  claim 11 , wherein the counting of the hold time comprises setting a hold time of the counter differently according to a transmission speed of a slave device. 
   
   
       20 . The method of  claim 11 , wherein the hold time is smaller than a time interval between a rising edge of the clock signal and the state transition of the SDA. 
   
   
       21 . A computer-readable recording medium storing a program for executing a method of controlling the timing of a state transition of a serial data line (SDA) in an I2C controller, the method comprising:
 detecting a falling edge of a clock signal of a serial clock line (SCL);   counting a hold time of the state transition of the SDA if the falling edge of the clock signal of the SCL is detected; and   transmitting the state of the SDA if the count of the hold time is finished.   
   
   
       22 . An I2C controller for controlling the timing of a state transition of a serial data line (SDA), the I2C controller comprising:
 a serial clock line SCL edge detector which detects an edge of a clock signal of an SCL;   a counter which counts a hold time of the state transition of the SDA when a falling edge of the clock signal of the SCL is detected by the SCL edge detector;   an SDA generator which transits a state of the SDA if the count of the hold time is finished; and   a processor which interfaces the SCL edge detector, the counter, and the SDA generator.   
   
   
       23 . A system-on-chip which controls the timing of a state transition of a serial data line (SDA), the system-on-chip comprising:
 a serial clock line SCL edge detector which detects an edge of a clock signal of an SCL;   a counter which counts a hold time of the state transition of the SDA when a falling edge of the clock signal of the SCL is detected by the SCL edge detector;   an SDA generator which transits a state of the SDA if the count of the hold time is finished; and   a processor which interfaces the SCL edge detector, the counter, and the SDA generator.