Semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

1 . A semiconductor memory device comprising:
 a memory cell array which has a plurality of memory cells arranged in matrix form, a plurality of word lines connected to the memory cells, and a plurality of bit lines connected to the memory cells;   a charge circuit which includes a plurality of charging transistors which charge the bit lines, respectively;   a bit line reset circuit which includes a plurality of resetting transistors respectively forcing potentials of the bit lines to a ground potential, and   a read circuit which includes a plurality of reading transistors whose gates are each connected directly to the bit lines and which outputs information according to the on and off states of the reading transistors.   
   
   
       2 . The semiconductor memory device according to  claim 1 , wherein:
 the charge circuit has a configuration in which the gates of the charging transistors are each connected to one of a plurality of decode signal lines for selecting the bit lines, and   the bit line reset circuit has a configuration in which the gates of the resetting transistors are each connected to one of a plurality of reset signal lines.   
   
   
       3 . The semiconductor memory device according to  claim 1  having a bit line precharge circuit which includes a plurality of precharging transistors which charge the bit lines for a fixed time period. 
   
   
       4 . The semiconductor memory device according to  claim 3 , wherein:
 the charge circuit has a configuration in which the gates of the charging transistors are each connected to one of a plurality of decode signal lines for selecting the bit lines;   the bit line precharge circuit has a configuration in which the gates of the precharging transistors are each connected to one of the precharge signal lines; and   the bit line reset circuit has a configuration in which the gates of the resetting transistors are each connected to one of a plurality of reset signal lines.   
   
   
       5 . The semiconductor memory device according to  claim 3 , wherein the charging transistors, the precharging transistors, the resetting transistors, and the reading transistors are N-type MOS transistors. 
   
   
       6 . The semiconductor memory device according to  claim 3 , wherein:
 the charge circuit includes a plurality of first operation controlling transistors which allow the charging transistors to effect charging operation, and   the precharge circuit includes a plurality of second operation controlling transistors which allow the precharging transistors to effect charging operation.   
   
   
       7 . The semiconductor memory device according to  claim 6 , wherein:
 the charge circuit has a configuration in which the charging transistors and the first operation controlling transistors are each connected to the bit lines in a state in which the individual charging transistors and the individual first operation controlling transistors are connected in series with each other,   the gates of the first operation controlling transistors are connected to an operation control signal line, and the gates of the charging transistors are connected to a plurality of decode signal lines,   the bit line precharge circuit has a configuration in which the precharging transistors and the second operation controlling transistors are each connected to the bit lines in a state in which the individual precharging transistors and the individual second operation controlling transistors are connected in series with each other,   the gates of the second operation controlling transistors are connected to the operation control signal line, and   the gates of the precharging transistors are each connected to a plurality of precharge signal lines, and   the bit line reset circuit has a configuration in which the gates of the resetting transistors are connected to a plurality of reset signal lines.   
   
   
       8 . A semiconductor storage system comprising:
 a plurality of memory blocks which each comprise a single semiconductor memory device and a logic circuit which logically synthesizes outputs from the memory blocks,   block selection signals being inputted to the individual operation control signal lines of the memory blocks as operation control signals,   wherein the single semiconductor memory device comprises:   a memory cell array which has a plurality of memory cells arranged in matrix form, a plurality of word lines connected to the memory cells, and a plurality of bit lines connected to the memory cells;   a charge circuit which includes a plurality of charging transistors which charge the bit lines, respectively;   a bit line reset circuit which includes a plurality of resetting transistors respectively forcing potentials of the bit lines to a ground potential,   a read circuit which includes a plurality of reading transistors whose gates are each connected directly to the bit lines and which outputs information according to the on and off states of the reading transistors, and   a bit line precharge circuit which includes a plurality of precharging transistors which charge the bit lines for a fixed time period,   wherein the charge circuit includes a plurality of first operation controlling transistors which allow the charging transistors to effect charging operation, and   the bit line precharge circuit includes a plurality of second operation controlling transistors which allow the precharging transistors to effect charging operation.   
   
   
       9 . The semiconductor memory device according to  claim 1  including:
 a bit line precharge circuit which includes a common precharging transistor, which charges the bit lines for a fixed time period, and   a plurality of selecting transistors which select the bit lines to be precharged from among the bit lines.   
   
   
       10 . The semiconductor memory device according to  claim 9 , wherein:
 the charge circuit has a configuration in which the gates of the charging transistors are each connected to one of a plurality of decode signal lines for selecting the bit lines,   the bit line precharge circuit has a configuration in which the gates of the selecting transistors are each connected to one of the decode signal lines for selecting the bit lines and in which the gate of the precharging transistor is connected to a precharge signal line, and   the bit line reset circuit has a configuration in which the gates of the resetting transistors are each connected to one of a plurality of reset signal lines.