Array transformation in a behavioral synthesis tool

Abstract

A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer is also provided the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.

1 .- 51 . (canceled) 
   
   
       52 . A method of interactively allocating memory in a behavioral synthesis tool, comprising:
 analyzing a source code description describing behavior of an integrated circuit, the source code description including one or more array variables;   representing the source code description in an intermediate format, the intermediate format including memory allocation information for the one or more array variables; and   allowing a user to change the memory allocation information for at least one of the one or more array variables while the source code description is represented in the intermediate format and before a register-transfer-level (RTL) description of the integrated circuit is generated using the memory allocation information.   
   
   
       53 . The method of  claim 52 , wherein the method further comprises providing a graphical user interface through which the user can indicate desired changes to the memory allocation information. 
   
   
       54 . The method of  claim 52 , further comprising modifying the memory allocation information in the intermediate format in response to changes input from the user. 
   
   
       55 . The method of  claim 52 , further comprising modifying the source code description in response to changes input from the user. 
   
   
       56 . The method of  claim 52 , wherein the memory allocation information for one of the one or more array variables includes an array length, and wherein the method further comprises changing the array length of the one of the one or more array variables in response to input from the user. 
   
   
       57 . The method of  claim 52 , wherein the memory allocation information for one of the one or more array variables includes an array width, and wherein the method further comprises changing the array width of the one of the one or more array variables in response to input from the user. 
   
   
       58 . The method of  claim 52 , wherein the memory allocation information for one of the one or more array variables includes a memory type, and wherein the method further comprises changing the memory type for the one of the one or more array variables in response to input from the user. 
   
   
       59 . The method of  claim 52 , wherein the memory allocation information for one of the one or more array variables includes a memory packing format, and wherein the method further comprises changing the memory packing format for the one of the one or more array variables in response to input from the user. 
   
   
       60 . The method of  claim 52 , further comprising displaying an area versus latency graph for at least one of the one or more array variables using current memory allocation information and before the RTL description of the integrated circuit is generated using the memory allocation information. 
   
   
       61 . The method of  claim 52 , further comprising generating an RTL description of the integrated circuit using the memory allocation information. 
   
   
       62 . A system, comprising:
 means for representing a source code description describing behavior of an integrated circuit in an intermediate format, the source code description including one or more array variables, and the intermediate format including memory allocation information for the one or more array variables; and   means for allowing a user to change the memory allocation information for at least one of the one or more array variables while the source code description is represented in the intermediate format and before a register-transfer-level (RTL) description of the integrated circuit is generated using the memory allocation information.   
   
   
       63 . The system of  claim 62 , further comprising means for modifying the memory allocation information in the intermediate format in response to changes input from the user. 
   
   
       64 . The system of  claim 62 , further comprising means for modifying the source code description in response to changes input from the user. 
   
   
       65 . A synthesis system, comprising:
 a memory storing an intermediate format representation of a source code description, the source code description and the intermediate format representation describing behavior of an integrated circuit and including one or more array variables; and   a graphical user interface that allows a user to modify memory allocation information for at least one of the one or more array variables before a register-transfer-level (RTL) description of the integrated circuit is generated using the memory allocation information.   
   
   
       66 . The synthesis system of  claim 65 , wherein the graphical user interface displays a list of processes associated with the source code description and array variables accessed with the processes. 
   
   
       67 . The synthesis system of  claim 65 , wherein the graphical user interface allows a user to modify an array length of at least one of the one or more array variables. 
   
   
       68 . The synthesis system of  claim 65 , wherein the graphical user interface allows a user to modify a memory type to allocated to at least one of the one or more array variables. 
   
   
       69 . The synthesis system of  claim 65 , wherein the graphical user interface allows a user to modify a memory packing format of at least one of the one or more array variables. 
   
   
       70 . The synthesis system of  claim 65 , further comprising a display configured to display an area versus latency graph for at least one of the one or more array variables using current memory allocation information and before the RTL description of the integrated circuit is generated using the memory allocation information. 
   
   
       71 . The synthesis system of  claim 65 , further comprising an RTL generator configured to generate an RTL description of the integrated circuit using the memory allocation information.