Discrete on-chip soi resistors

Abstract

A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.

1 . An integrated circuit (IC) chip including at least one semiconductor resistor, said IC chip comprising:
 a semiconductor body of a first conductive type;   a well of a second conductive type in a surface of said semiconductor body;   at least two trenches in said surface of said well, said at least two trenches being filled with dielectric;   a resistive pillar between each pair of trenches; and   a contact at either end of said resistive pillar.   
   
   
       2 . A (IC) chip as in  claim 1 , wherein said semiconductor body is a silicon substrate of a silicon on insulator (SOI) wafer and said well is a buried well in said silicon substrate beneath a silicon island in a silicon surface layer of said SOI wafer. 
   
   
       3 . A (IC) chip as in  claim 2 , wherein said at least two trenches extend through said silicon island and an oxide layer beneath said silicon island and 0.1-1.0 μm into said buried well. 
   
   
       4 . A (IC) chip as in  claim 2 , wherein said buried well is a layered well. 
   
   
       5 . A (IC) chip as in  claim 1 , further comprising:
 a dielectric material layer beneath each said resistive pillar.   
   
   
       6 . A (IC) chip as in  claim 2 , wherein said substrate is P-type silicon, said well is N-type and said sidewall resistor comprises a N-type dopant layer in said each sidewall. 
   
   
       7 . A (IC) chip as in  claim 1 , further comprising dielectric material filling each of said at least two trenches to an upper surface of said silicon island. 
   
   
       8 . A (IC) chip as in  claim 1 , further comprising:
 an outboard isolation trench around the perimeter of one or more at least one semiconductor resistor.   
   
   
       9 . A (IC) chip as in  claim 8 , further wherein said outboard isolation trench is at the perimeter of said well. 
   
   
       10 . A (IC) chip as in  claim 1 , wherein said at least two trenches comprises three or more trenches forming parallel resistive pillars. 
   
   
       11 . A CMOS silicon on insulator (SOI) integrated circuit (IC) chip including at least one semiconductor resistor, said IC chip comprising:
 a silicon surface layer on an oxide layer, said oxide layer on a silicon substrate of a first conduction type;   a buried well of a second conduction type in a surface of said silicon substrate, said buried well being beneath a silicon island in said silicon surface layer;   at least two trenches in said silicon island and said buried well, said at least two trenches being filled with dielectric to an upper surface of said silicon island;   a resistive pillar of said second conduction type in said buried well between each pair of trenches; and   a contact at either end of said resistive pillar.   
   
   
       12 . A (IC) chip as in  claim 11 , wherein said at least two trenches extend 0.1-1.0 μm into said buried well. 
   
   
       13 . A (IC) chip as in  claim 11 , wherein said buried well is a layered well. 
   
   
       14 . A (IC) chip as in  claim 11 , further comprising:
 a dielectric material layer beneath each said resistive pillar.   
   
   
       15 . A (IC) chip as in  claim 11 , wherein said substrate is P-type silicon, said well is N-type and said sidewall resistor comprises a N-type dopant layer in said each sidewall. 
   
   
       16 . A (IC) chip as in  claim 11 , further comprising:
 an outboard isolation trench around the perimeter of one or more at least one semiconductor resistor.   
   
   
       17 . A (IC) chip as in  claim 16 , further wherein said outboard isolation trench is at the perimeter of said well. 
   
   
       18 . A (IC) chip as in  claim 11 , wherein at least one semiconductor resistor comprises a plurality of silicon resistors, and in at least one of said plurality of silicon resistors said at least two trenches comprises three or more trenches forming parallel resistive pillars.