semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

1 . A semiconductor integrated circuit device, comprising:
 a semiconductor substrate;   a plurality of I/O cells formed in the semiconductor substrate;   a power wire for supplying an operation power to the I/O cell, the power wire being formed of a plurality of interconnect layers over the I/O cells;   a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and   a lead-out area for electrically coupling the I/O cell to the bonding pad,   wherein the power wire includes:
 a first power wire to be set to a high-potential-side supply voltage level; and 
 a second power wire to be set to a ground level; 
   wherein the I/O cell includes:
 a first element coupled to the first power wire; and 
 a second element coupled to the second power wire; and 
   wherein the first element is placed on the first power wire side and the second element is placed on the second power wire side.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein the lead-out area includes:
 a first lead-out area for electrically coupling the I/O cell from the first power wire side to the bonding pad; and   a second lead-out area for electrically coupling the I/O cell from the second power wire side to the bonding pad.   
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , further comprising a plurality of interconnect layers between the I/O cell and the bonding pad,
 wherein the first power wire and the second power wire are formed of the interconnect layers excluding a interconnect layer directly under the bonding pad.   
     
     
         4 . The semiconductor integrated circuit device according to  claim 1 , wherein the first element includes:
 a p-channel type MOS transistor for outputting data; and   a first diode element for protecting the p-channel type MOS transistor; and   wherein the second element includes:
 an n-channel type MOS transistor for outputting data and 
 a second diode element for protecting the n-channel type MOS transistor. 
   
     
     
         5 . The semiconductor integrated circuit device according to  claim 4 , wherein the I/O cell includes:
 a first protective resistance element coupled between the p-channel type MOS transistor and the first diode element; and   a second protective resistance element coupled between the n-channel type MOS transistor and the second diode element.   
     
     
         6 . The semiconductor integrated circuit device according to  claim 4 , wherein the I/O cell includes
 a pre-buffer for driving the p-channel type MOS transistor and n-channel type MOS transistor based on data to be output.   
     
     
         7 . The semiconductor integrated circuit device according to  claim 1 , further comprising:
 a power cell for taking in a power supply;   a power-supply bonding pad formed over the power cell; and   a power-supply lead-out area for electrically coupling the power cell to the power-supply bonding pad,   wherein the power cell includes protective elements for protecting a circuit from surge; and   wherein among the protective elements the one coupled to the power wire is placed in the vicinity of the power wire.