Dynamic random access memory cell and manufacturing method thereof

Abstract

A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.

1 . A manufacturing method of a dynamic random access memory cell, comprising:
 providing a substrate;   forming a bottom oxide and a semiconductor layer on the substrate, wherein the semiconductor layer is formed on the bottom oxide layer;   forming a gate on the semiconductor layer;   patterning the semiconductor layer to expose a portion of the bottom oxide layer;   forming an insulation layer at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than the height of the side walls of the semiconductor layer, so that a gap is formed between the tops of the semiconductor layer and the insulation layer; and   forming a doping layer on the bottom oxide layer, wherein the doping layer covers the insulation layer and has the same height with the semiconductor layer, and the doping layer contacts the side walls of the semiconductor layer via the gap.   
   
   
       2 . The manufacturing method according to  claim 1 , wherein the step of forming the gate comprises:
 forming a gate oxide layer on the semiconductor layer;   forming an electrode layer on the gate oxide layer;   forming a buffer layer on the electrode layer;   forming a mask layer on the buffer layer;   patterning the buffer layer and the mask layer; and   patterning the electrode layer and the gate oxide layer so as to form the gate.   
   
   
       3 . The manufacturing method according to  claim 2 , wherein the electrode layer is made from N-type doped poly-silicon. 
   
   
       4 . The manufacturing method according to  claim 3 , wherein the cell is an N-channel metal oxide semiconductor (NMOS) structure. 
   
   
       5 . The manufacturing method according to  claim 2 , wherein the electrode layer is made from P-type doped poly-silicon. 
   
   
       6 . The manufacturing method according to  claim 5 , wherein the cell is a P-channel metal oxide semiconductor structure. 
   
   
       7 . The manufacturing method according to  claim 2 , wherein the buffer layer is made from silicon dioxide (SiO 2 ). 
   
   
       8 . The manufacturing method according to  claim 2 , wherein the mask layer is made from silicon nitride (Si 3 N 4 ). 
   
   
       9 . The manufacturing method according to  claim 2 , wherein after the step of forming the doping layer, the method further comprises:
 removing the mask layer and the buffer layer.   
   
   
       10 . The manufacturing method according to  claim 1 , wherein the step of forming the insulation layer comprises:
 forming an oxide layer on the bottom oxide layer, wherein the oxide layer covers the bottom oxide layer, the semiconductor layer and the gate; and   etching the oxide layer for forming the gap between the tops of the semiconductor layer and the oxide layer, wherein the etched oxide layer is the insulation layer.   
   
   
       11 . The manufacturing method according to  claim 10 , wherein the oxide layer is formed on the bottom oxide layer by way of plasma assisted chemical vapor deposition (PACVD). 
   
   
       12 . The manufacturing method according to  claim 1 , wherein the step of forming the insulation layer comprises:
 forming a nitride layer on the surface of the bottom oxide layer, the semiconductor layer and the gate;   removing the nitride layer positioned on the top surface of the gate;   forming an oxide layer on the bottom oxide layer, wherein the oxide layer covers the bottom oxide layer, the nitride layer and the top surface of the gate;   etching the oxide layer for exposing a portion of the nitride layer, wherein the height of the oxide layer is slightly shorter than the height of the semiconductor layer;   etching the nitride layer exposed outside the oxide layer for forming the gap between the tops of the semiconductor layer and the nitride layer, wherein the etched nitride layer is the insulation layer; and   removing the oxide layer.   
   
   
       13 . The manufacturing method according to  claim 12 , wherein the oxide layer is formed on the bottom oxide layer by way of plasma assisted chemical vapor deposition. 
   
   
       14 . The manufacturing method according to  claim 12 , wherein the nitride layer positioned on the top surface of the mask layer is removed by way of chemical mechanical polishing (CMP) or etching back process. 
   
   
       15 . The manufacturing method according to  claim 1 , wherein the step of forming the doping layer comprises:
 forming a silicon layer on the bottom oxide layer, wherein the silicon layer is disposed at the two sides of the semiconductor layer and the gate and covers the insulation layer, and the silicon layer contacts the side walls of the semiconductor layer via the gap;   etching the silicon layer for the silicon layer to have the same height with the semiconductor layer; and   doping a dopant into the silicon layer.   
   
   
       16 . The manufacturing method according to  claim 15 , wherein the silicon layer is formed on the bottom oxide layer by way of chemical vapor deposition. 
   
   
       17 . The manufacturing method according to  claim 15 , wherein the dopant is doped into the silicon layer by ion implantation. 
   
   
       18 . The manufacturing method according to  claim 1 , wherein the gap is 5 nm at most. 
   
   
       19 . A dynamic random access memory cell, comprising:
 a bottom oxide layer disposed on a substrate;   a semiconductor layer disposed on the bottom oxide layer, wherein the semiconductor layer covers a portion of the bottom oxide layer;   an insulation layer disposed at the side walls of the semiconductor layer, wherein the height of the insulation layer is different from the height of the semiconductor layer, so that a gap is formed between the tops of the semiconductor layer and the insulation layer;   a doping layer disposed on the bottom oxide layer, wherein the doping layer has the same height with the semiconductor layer, and the doping layer contacts the side walls of the semiconductor layer via the gap; and   a gate disposed on the semiconductor layer.   
   
   
       20 . The cell according to  claim 19 , wherein the gate comprises:
 a gate oxide layer disposed on the semiconductor layer; and   an electrode layer disposed on the gate oxide layer.   
   
   
       21 . The cell according to  claim 20 , wherein the electrode layer is made from N-type doped poly-silicon. 
   
   
       22 . The cell according to  claim 21 , is an N-channel metal oxide semiconductor structure. 
   
   
       23 . The cell according to  claim 20 , wherein the electrode layer is made from P-type doped poly-silicon. 
   
   
       24 . The cell according to  claim 23 , being a P-channel metal oxide semiconductor structure. 
   
   
       25 . The cell according to  claim 20 , wherein the gate oxide layer is made from silicon dioxide (SiO 2 ). 
   
   
       26 . The cell according to  claim 19 , wherein the insulation layer is made from dielectric material. 
   
   
       27 . The cell according to  claim 26 , wherein the insulation layer is an oxide layer or a nitride layer. 
   
   
       28 . The cell according to  claim 19 , wherein the gap is 5 nm at most. 
   
   
       29 . The cell according to  claim 19 , wherein the doping layer is the source and the drain of the cell.