Programmable Non-Volatile Resistance Switching Device

Abstract

A memory element comprises a first number of electrodes and a second number of electrically conducting channels between sub-groups of two of said electrodes, the channels exhibiting an electrical resistance that is reversibly switchable between different states, wherein the first number is larger than two and the second number is larger than the first number divided by two. The electrically conducting channels may be provided in transition metal oxide material, which exhibits a reversibly switchable resistance that is attributed to a switching phenomenon at the interfaces between the electrodes and the transition metal oxide material.

1 . An interconnected memory cell element comprising an interconnected memory cell micro-electronic device having a first number of electrodes and a second number of electrically conducting programmable resistance channels forming interconnecting programmable resistance paths between the electrodes for interface resistive switching, each one of said programmable resistance channels connecting one of said electrodes to another one of said electrodes wherein said device has programmable resistance channels formed between pairs of electrodes opposed to each other in the manner of capacitors and said device has a conducting programmable resistance channel between two electrodes arranged side by side for interconnection in said interconnected memory cell, the programmable resistance channels exhibiting an electrical programmable resistance that is reversibly switchable between different states for interface resistive switching, wherein the first number is larger than two and the second number is larger than the first number divided by two, and said electrodes are provided adjacent a transition metal oxide material and interconnected thereby, said transition metal oxide material forming part of said electrically conducting programmable resistance channels providing interface resistive switching due to the electronic state of the transition metal oxide material in the interface of the programmable resistance channels between the electrodes and said transition metal oxide. 
     
     
         2 . The interconnected memory cell element of  claim 1 , wherein the transition metal oxide material comprises a transition metal dopant either of one transition metal or a combination of different transition metals. 
     
     
         3 . The interconnected memory cell element of  claim 1 , wherein the transition metal oxide material is a perovskite material. 
     
     
         4 . The interconnected memory cell element of  claim 2 , wherein said transition metal dopant is selected from the group consisting of Chromium, Vanadium, and Manganese. 
     
     
         5 . The interconnected memory cell of  claim 1  wherein the transition metal oxide material is provided as a layer and the electrodes are arranged at different sides of said layer such that said pairs of said electrodes function as capacitors. 
     
     
         6 . The interconnected memory cell of  claim 1 , wherein the electrically conducting programmable resistance channels are conduits formed by a formation process which includes applying a voltage during the formation process. 
     
     
         7 . The interconnected memory cell element of  claim 1  wherein said first number is at least four and a first one of said programmable resistance channels connects a first one of said electrodes with a second one of said electrodes, a second one of said programmable resistance channels connects the second electrode to a third one of said electrodes, and a third one of said programmable resistance channels connects the third electrode to a forth one of said electrodes. 
     
     
         8 . The interconnected memory cell of  claim 7 , wherein said at least four electrodes are provided adjacent a layer of transition metal oxide material that forms said electrically conducting programmable resistance channels, said second and said third electrode being provided on a first side of said layer, and said first and forth electrode being provided on a second side of said layer.