Nonvolatile memory with error correction for page copy operation and method thereof

Abstract

The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

1 - 9 . (canceled) 
   
   
       10 . A method of transferring source data of a first position to a second position in a memory system, the memory system comprising a nonvolatile memory including a memory cell array and a buffer, the method comprising:
 receiving a first command and address;   storing the source data of the first position of the memory cell array into the buffer in response to the first command and address;   detecting a bit error of the source data stored in the buffer;   correcting the bit error when it is detected;   receiving a second command and address; and   copying the corrected source data to the second position of the memory cell array in response to the second command and address, after the correcting.   
   
   
       11 . The method as recited in  claim 10 , wherein the receiving a first command and address, the storing, the detecting, the correcting, the receiving a second command and address, and the copying are sequentially performed. 
   
   
       12 . The method as recited in  claim 10 , further comprising:
 copying the source data stored in the buffer to the second position when the bit error is not detected.   
   
   
       13 . The method as recited in  claim 10 , wherein the first command and address, and the second command and address are sequentially inputted to the nonvolatile memory. 
   
   
       14 . The method as recited in  claim 10 , wherein the memory cell array has a plurality of pages, wherein each of the first and second positions is a page. 
   
   
       15 . A method of transferring source data of a first position to a second position in a memory system, the memory system comprising a nonvolatile memory including a buffer and a memory controller to control the nonvolatile memory, the method comprising:
 providing a read command and a first address to the nonvolatile memory from the memory controller in order to store the source data of the first position of the nonvolatile memory into the buffer;   detecting a bit error of the source data stored in the buffer;   correcting the bit error when it is detected; and   providing a write command and a second address to the nonvolatile memory from the memory controller in order to copy the corrected source data to the second position of the nonvolatile memory, after the correcting.   
   
   
       16 . The method as recited in  claim 15 , wherein the providing a read command, the detecting, the correcting, and the providing a write command are sequentially performed. 
   
   
       17 . The method as recited in  claim 15 , wherein the memory controller controls the detecting and correcting operation. 
   
   
       18 . The method as recited in  claim 15 , further comprising:
 copying the source data stored in the buffer to the second position of the nonvolatile memory when the bit error is not detected.   
   
   
       19 . The method as recited in  claim 15 , wherein the nonvolatile memory comprises a memory cell array having a plurality of pages, wherein each of the first and second positions is a page. 
   
   
       20 . A memory system comprising:
 a nonvolatile memory cell array storing source data in a first position;   a buffer temporarily storing the source data of the first position; and   an error correction circuit for detecting a bit error of the source data stored in the buffer and for correcting the bit error when it is detected;   wherein the corrected source data is copied to a second position of the nonvolatile memory cell array after the error correction.   
   
   
       21 . The memory system of  claim 20 , wherein the source data stored in the buffer is copied to the second position when the bit error is not detected. 
   
   
       22 . The memory system of  claim 20 , wherein the source data stored in the buffer is transferred to the error correction circuit through input/output lines before the error detection. 
   
   
       23 . The memory system of  claim 20 , wherein the error correction circuit generates old parities from the source data before storing the source data of the first position into the buffer, generates new parities from the source data stored in the buffer; compares the old parities with the new parities, and corrects the bit error of the source data stored in the buffer in response to a result of the comparison. 
   
   
       24 . The memory system of  claim 23 , wherein the source data stored in the buffer is transferred to the error correction circuit through input/output lines before the generation of the new parities. 
   
   
       25 . The memory system of  claim 20 , wherein the nonvolatile memory cell array comprises a plurality of pages, wherein each of the first and second positions is a page. 
   
   
       26 . A method of transferring source data of a first position to a second position in a memory system, the memory system comprising a nonvolatile memory including a memory cell array and a buffer, the method comprising:
 storing the source data of the first position of the memory cell array into the buffer;   detecting a bit error of the source data stored in the buffer;   correcting the bit error when it is detected; and   copying the corrected source data to the second position of the memory cell array after the correcting.   
   
   
       27 . The method as recited in  claim 26 , further comprising:
 copying the source data stored in the buffer to the second position when the bit error is not detected.   
   
   
       28 . The method as recited in  claim 26 , wherein the storing, the detecting, the correcting, and the copying are performed sequentially. 
   
   
       29 . The method as recited in  claim 26 , further comprising:
 transferring the source data stored in the buffer to an error correction circuit through input/output lines before the detecting.   
   
   
       30 . The method as recited in  claim 26 , further comprising:
 generating old parities from the source data before storing the source data of the first position into the buffer.   
   
   
       31 . The method as recited in  claim 30 , wherein detecting the bit error of the stored source data comprises:
 generating new parities from the source data stored in the buffer; and   comparing the old parities with the new parities.   
   
   
       32 . The method as recited in  claim 31 , further comprising:
 transferring the source data stored in the buffer to an error correction circuit through input/output lines before the generating new parities.   
   
   
       33 . The method as recited in  claim 31 , wherein the correcting is performed to correct the bit error of the source data stored in the buffer in response to a result of the comparing. 
   
   
       34 . The method as recited in  claim 31 , further comprising:
 informing an error status by providing the comparing result outside of the memory system.   
   
   
       35 . The method as recited in  claim 26 , wherein the bit error is a progressive bit error. 
   
   
       36 . The method as recited in  claim 26 , wherein the nonvolatile memory is a NAND flash memory. 
   
   
       37 . The method as recited in  claim 36 , wherein the NAND flash memory comprises a memory cell array having a plurality of pages, wherein each of the first and second positions is a page.